公开(公告)号：US20240249753A1

公开(公告)日：2024-07-25

申请号：US18509039

申请日：2023-11-14

申请人： SK hynix Inc.

发明人： Choung Ki SONG

IPC分类号： G11C7/10 ,  G11C7/22

CPC分类号： G11C7/1039 ,  G11C7/1063 ,  G11C7/222 ,  H01L2224/08111 ,  H01L2224/08145 ,  H01L2224/48132 ,  H01L2224/48147 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H10B80/00

摘要： A buffer chip includes: a chip select signal reception circuit configured to receive chip select signals transmitted from a memory controller; a command address reception circuit configured to receive command address signals transmitted from the memory controller; a chip select signal transmission circuit configured to transmit the chip select signals to a plurality of memory chips; a command address transmission circuit configured to transmit the command address signals to the plurality of memory chips; and a command address fixing circuit configured to fix levels of at least one of the command address signals transmitted by the command address transmission circuit when the chip select signals are deactivated for a predetermined time or more.

公开(公告)号：US20240170412A1

公开(公告)日：2024-05-23

申请号：US18367626

申请日：2023-09-13

申请人： NANYA TECHNOLOGY CORPORATION

发明人： WU-DER YANG

IPC分类号： H01L23/544 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/544 ,  H01L21/78 ,  H01L22/32 ,  H01L23/5381 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/5446 ,  H01L2224/48132

摘要： A memory device package and a method of manufacturing a memory device package. The memory device package includes a substrate having a first chip region, a second chip region, and a first scribe line region connected between the first chip region and the second chip region. The memory device package also includes a first memory chip disposed over the first chip region and a second memory chip disposed over the second chip region.

公开(公告)号：US11948913B2

公开(公告)日：2024-04-02

申请号：US17519917

申请日：2021-11-05

申请人： Samsung Electronics Co., Ltd.

发明人： Seunghyun Baik

IPC分类号： H01L25/065 ,  H01L23/00

CPC分类号： H01L25/0652 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/33 ,  H01L24/45 ,  H01L2224/05541 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/0569 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06165 ,  H01L2224/06515 ,  H01L2224/32013 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/48132 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265

摘要： A semiconductor package according to the exemplary embodiments of the disclosure includes a base substrate including a base bonding pad, a first semiconductor chip disposed on the base substrate, a first adhesive layer provided under the first semiconductor chip, a first bonding pad provided in a bonding region on an upper surface of the first semiconductor chip, a first bonding wire interconnecting the base bonding pad and the first bonding pad, and a crack preventer provided in a first region at the upper surface of the first semiconductor chip. The crack preventer includes dummy pads provided at opposite sides of the first region and a dummy wire interconnecting the dummy pads.

公开(公告)号：US09881892B2

公开(公告)日：2018-01-30

申请号：US15412072

申请日：2017-01-23

申请人： Novatek Microelectronics Corp.

发明人： Jung-Fu Hsu ,  Tai-Hung Lin ,  Chang-Tien Tsai

IPC分类号： H01L21/02 ,  H01L23/00 ,  H01L27/02 ,  H01L23/50

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L23/60 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0248 ,  H01L27/0292 ,  H01L27/0296 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05088 ,  H01L2224/05095 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/0612 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48132 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/2064 ,  H01L2924/30205 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/43

摘要： An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, a third bonding pad structure, a first internal bonding wire, and a second internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The third bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the third bonding pad structure via the first internal bonding wire. The third bonding pad structure is electrically coupled to the second bonding pad structure via the second internal bonding wire.

公开(公告)号：US20170133343A1

公开(公告)日：2017-05-11

申请号：US15412072

申请日：2017-01-23

申请人： Novatek Microelectronics Corp.

发明人： Jung-Fu Hsu ,  Tai-Hung Lin ,  Chang-Tien Tsai

IPC分类号： H01L23/00 ,  H01L23/50 ,  H01L27/02

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L23/60 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0248 ,  H01L27/0292 ,  H01L27/0296 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05088 ,  H01L2224/05095 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/0612 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48132 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/2064 ,  H01L2924/30205 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/43

摘要： An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, a third bonding pad structure, a first internal bonding wire, and a second internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The third bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the third bonding pad structure via the first internal bonding wire. The third bonding pad structure is electrically coupled to the second bonding pad structure via the second internal bonding wire.

公开(公告)号：US09576891B1

公开(公告)日：2017-02-21

申请号：US14872692

申请日：2015-10-01

申请人： Avago Technologies General IP (Singapore) Pte. Ltd.

发明人： Qian Tao ,  Richard Lum Kok Keong ,  Boon Keat Tan

IPC分类号： H01L29/00 ,  H01L23/522

CPC分类号： H01L25/0657 ,  H01L23/48 ,  H01L23/5223 ,  H01L23/5283 ,  H01L24/13 ,  H01L24/46 ,  H01L25/0655 ,  H01L29/0649 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/48091 ,  H01L2224/48132 ,  H01L2224/48463 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2924/00014 ,  H01L2224/45099

摘要： An isolation device for isolating a first signal of a first circuit from a second circuit disclosed. The isolation device may have a substrate and a plurality of metal layers disposed on the substrate. The plurality of metal layers have a topmost metal layer disposed furthest away from the substrate and a first interconnect metal layer formed nearest to the substrate. The first interconnect metal layer is disposed at a first distance away from the substrate, whereas the topmost metal layer is disposed at an isolation distance away from a first adjacent metal layer formed nearest to the topmost metal layer. A portion of the topmost metal layer forms a first plate. The first plate is configured to transmit the first signal from the first circuit to a second plate that is connected to the second circuit, but electrically isolated from the first plate.

摘要翻译： 一种用于将第一电路的第一信号与所公开的第二电路隔离的隔离装置。 隔离装置可以具有衬底和设置在衬底上的多个金属层。 多个金属层具有最远离衬底设置的最顶层金属层和最靠近衬底形成的第一互连金属层。 第一互连金属层设置在远离基板的第一距离处，而最顶层金属层设置在隔离距离远离最靠近最顶层金属层形成的第一相邻金属层。 最顶层金属层的一部分形成第一板。 第一板被配置为将第一信号从第一电路传输到连接到第二电路但与第一板电隔离的第二板。

公开(公告)号：US20160141284A1

公开(公告)日：2016-05-19

申请号：US14897362

申请日：2013-08-23

申请人： MITSUBISHI ELECTRIC CORPORATION

发明人： Mikio ISHIHARA ,  Kazuaki HIYAMA ,  Tatsuya KAWASE ,  Tsuyoshi OSAGA

IPC分类号： H01L27/02 ,  H01L23/34 ,  H01L27/06 ,  H01L23/00

CPC分类号： H01L27/0251 ,  H01L23/34 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L2224/0603 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48132 ,  H01L2224/4846 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H03K17/0828 ,  H03K2017/0806 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A transistor (2) is provided on a semiconductor substrate (8). A temperature detection diode (4) for monitoring temperature of an upper surface of the semiconductor substrate (8) is provided on the semiconductor substrate (8). An external electrode (7) is connected in common to an emitter (E) of the transistor (2) and a cathode (K) of the temperature detection diode (4). Therefore, an external electrode for the cathode (K) of the temperature detection diode (4) can be removed, and thus the device can be reduced in size and improved in terms of ease of assembly.

摘要翻译： 晶体管（2）设置在半导体衬底（8）上。 用于监测半导体衬底（8）的上表面的温度的温度检测二极管（4）设置在半导体衬底（8）上。 外部电极（7）共同连接到晶体管（2）的发射极（E）和温度检测二极管（4）的阴极（K）。 因此，可以去除用于温度检测二极管（4）的阴极（K）的外部电极，因此可以减小装置的尺寸并且在组装的容易性方面得到改进。

公开(公告)号：US08446726B2

公开(公告)日：2013-05-21

申请号：US12914171

申请日：2010-10-28

申请人： Ralf Schloerke ,  Thilo Stolze

发明人： Ralf Schloerke ,  Thilo Stolze

IPC分类号： H05K7/20 ,  H01L23/34 ,  F28F7/00

CPC分类号： H01L23/24 ,  H01L23/10 ,  H01L23/367 ,  H01L23/3735 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/34 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/072 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48132 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/8384 ,  H01L2224/8584 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  Y10T29/41 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A power semiconductor module includes a module housing with a sealing ring on its top side. The sealing ring, in co-operation with the module housing and a printed circuit board attached to the power semiconductor module, hermetically seals feed-through locations at the top side of the module housing for feeding through electric terminals of the power semiconductor module. On the bottom side of the module housing a sealing ring hermetically seals the bottom side of the module housing.

摘要翻译： 功率半导体模块包括在其顶侧具有密封环的模块壳体。 与模块壳体配合的密封环和连接到功率半导体模块的印刷电路板密封地密封模块壳体顶侧的馈通位置，以通过功率半导体模块的电端子供电。 在密封环的模块的底侧上，密封环密封模块壳体的底侧。

公开(公告)号：US08253247B2

公开(公告)日：2012-08-28

申请号：US12756208

申请日：2010-04-08

申请人： Noriko Numata ,  Hiroshi Sato ,  Toru Ueguri

发明人： Noriko Numata ,  Hiroshi Sato ,  Toru Ueguri

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L29/7813 ,  H01L23/4824 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/77 ,  H01L24/78 ,  H01L24/84 ,  H01L24/85 ,  H01L24/97 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/7811 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/40091 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48132 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/49171 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/78 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85205 ,  H01L2224/85399 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00015 ,  H01L2924/00012

摘要： In a method for manufacturing a semiconductor device involving the step of bonding a metallic ribbon to a pad of a semiconductor chip, breakage of the metallic ribbon is to be prevented while ensuring the bonding strength even when the metallic ribbon becomes thin with reduction in size of the semiconductor chip. In bonding an Al ribbon to a pad of a semiconductor chip by bringing a pressure bonding surface of a wedge tool into pressure contact with the Al ribbon while applying ultrasonic vibration to the ribbon positioned over the pad, recesses 10a are formed beforehand at both end portions respectively of the wedge tool lest both end portions in the width direction of the Al ribbon bonded to the pad should contact the pressure bonding surface of the wedge tool.

摘要翻译： 在涉及将金属带接合到半导体芯片的焊盘的步骤的半导体器件的制造方法中，即使当金属带变薄时，也可以确保金属带的断裂，同时确保接合强度，同时尺寸减小 半导体芯片。 通过使楔形工具的压接面与Al带压接，同时对位于焊盘上的带施加超声波振动，将Al带接合到半导体芯片的焊盘，在两端部预先形成有凹部10a 分别与楔形工具接合的Al带的宽度方向上的两个端部应接触楔形工具的压接表面。

公开(公告)号：US20240170410A1

公开(公告)日：2024-05-23

申请号：US18056549

申请日：2022-11-17

申请人： NANYA TECHNOLOGY CORPORATION

发明人： WU-DER YANG

IPC分类号： H01L23/544 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/544 ,  H01L21/78 ,  H01L22/32 ,  H01L23/5381 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/5446 ,  H01L2224/48132

摘要： A memory device package and a method of manufacturing a memory device package. The memory device package includes a substrate having a first chip region, a second chip region, and a first scribe line region connected between the first chip region and the second chip region. The memory device package also includes a first memory chip disposed over the first chip region and a second memory chip disposed over the second chip region.