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    Semiconductor package
    1.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11581290B2

    公开(公告)日：2023-02-14

    申请号：US17167538

    申请日：2021-02-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seunghyun Baik

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528

    Abstract: A semiconductor package includes a package substrate including an insulating layer having an upper surface and a lower surface and provided with a first region which is recessed to a first depth from the upper surface toward the lower surface, a redistribution wiring buried in the insulating layer, a chip connection pad on a bottom surface of the recessed first region and connected to the redistribution wiring, and a wire connection pad on the upper surface of the insulating layer and connected to the redistribution wiring, a first semiconductor chip overlapping, in a top-down view of the semiconductor package, the recessed first region of the insulating layer and comprising a first chip pad connected to the chip connection pad of the package substrate, and a second semiconductor chip on the first semiconductor chip and connected to the wire connection pad of the package substrate through a conductive wire.

    SEMICONDUCTOR PACKAGE
    2.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220013500A1

    公开(公告)日：2022-01-13

    申请号：US17167538

    申请日：2021-02-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seunghyun Baik

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L23/31

    Abstract: A semiconductor package includes a package substrate including an insulating layer having an upper surface and a lower surface and provided with a first region which is recessed to a first depth from the upper surface toward the lower surface, a redistribution wiring buried in the insulating layer, a chip connection pad on a bottom surface of the recessed first region and connected to the redistribution wiring, and a wire connection pad on the upper surface of the insulating layer and connected to the redistribution wiring, a first semiconductor chip overlapping, in a top-down view of the semiconductor package, the recessed first region of the insulating layer and comprising a first chip pad connected to the chip connection pad of the package substrate, and a second semiconductor chip on the first semiconductor chip and connected to the wire connection pad of the package substrate through a conductive wire.

    SEMICONDUCTOR PACKAGE
    6.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20240395755A1

    公开(公告)日：2024-11-28

    申请号：US18437895

    申请日：2024-02-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seunghyun Baik

    IPC: H01L23/00

    Abstract: Some embodiments of the present disclosure provide a semiconductor package including: a package substrate including a main pad and a main wiring pattern; a semiconductor chip on the package substrate; a plurality of connection bumps between the package substrate and the semiconductor chip and including a plurality of connection solder patterns on the main pad and a plurality of connection pillars on the connection solder patterns; a dummy insulating pattern between the package substrate and the semiconductor chip and configured to cover the main wiring pattern; and a plurality of dummy pillars on the dummy insulating pattern, wherein the dummy pillars are in contact with the dummy insulating pattern, and are electrically insulated from the dummy insulating pattern.

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