公开(公告)号：US12113028B2

公开(公告)日：2024-10-08

申请号：US17556149

申请日：2021-12-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tse-Yao Huang

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/544 ,  H01L23/5222 ,  H01L23/5386 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/8313 ,  H01L2225/06593

Abstract: The present application discloses a semiconductor device with integrated decoupling alignment features. The semiconductor device includes a first wafer comprising a first substrate having a dielectric stack, a decoupling feature positioned in the dielectric stack under one of the plurality of first alignment marks, a plurality of first alignment marks positioned on the first substrate and parallel to each other; and a second wafer positioned on the first wafer and comprising a plurality of second alignment marks positioned above the plurality of first alignment marks. The plurality of second alignment marks are arranged parallel to the plurality of first alignment marks and adjacent to the plurality of first alignment marks in a top-view perspective. The plurality of first alignment marks and the plurality of second alignment marks comprise a fluorescence material. The decoupling feature has a bottle-shaped cross-sectional profile, and the decoupling feature comprises a porous low-k material.

公开(公告)号：US11854999B2

公开(公告)日：2023-12-26

申请号：US17880862

申请日：2022-08-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Xin-Hua Huang ,  Ping-Yin Liu

IPC: H01L23/544 ,  H01L23/00 ,  B23Q17/22 ,  H01L21/18 ,  H01L21/68 ,  H01L25/065

CPC classification number: H01L23/544 ,  H01L24/83 ,  B23Q17/22 ,  H01L21/187 ,  H01L21/681 ,  H01L24/81 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/8313

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes bonding structure arranged directly between a first substrate and a second substrate. The first substrate includes a first transparent material and a first alignment mark. The first alignment mark is arranged on an outer region of the first substrate and also includes the first transparent material. The first alignment mark is defined by surfaces of the first substrate that are arranged between an uppermost surface of the first substrate and a lowermost surface of the first substrate. The second substrate includes a second alignment mark on an outer region of the second substrate. The second alignment mark directly underlies the first alignment mark, and the bonding structure is arranged directly between the first alignment mark and the second alignment mark.

公开(公告)号：US20230378121A1

公开(公告)日：2023-11-23

申请号：US18318836

申请日：2023-05-17

Applicant: Tokyo Electron Limited

Inventor： Yuhei Matsuo

IPC: H01L23/00 ,  H04N23/56 ,  H04N23/90 ,  G06T7/73 ,  G06T7/00 ,  H04N23/10 ,  G06T7/90

CPC classification number: H01L24/75 ,  H01L24/94 ,  H01L24/83 ,  H04N23/56 ,  H04N23/90 ,  G06T7/73 ,  G06T7/0004 ,  H04N23/10 ,  G06T7/90 ,  H01L24/32 ,  H01L24/29 ,  H01L2224/29186 ,  H01L2924/0544 ,  H01L2924/0504 ,  H01L2924/059 ,  H01L2224/94 ,  H01L2224/32145 ,  H01L2224/75701 ,  H01L2224/75702 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75753 ,  H01L2224/7598 ,  H01L2224/8313 ,  H01L2224/8316 ,  H01L2224/83896 ,  H01L2224/8301 ,  H01L2224/7501 ,  G06T2207/30204 ,  G06T2207/30148 ,  G06T2207/10024 ,  G06T2207/10152

Abstract: A bonding apparatus bonds a first substrate having a first alignment mark and a second substrate having a second alignment mark. A first radiation unit radiates white light to an imaging area of a first imaging unit when the second alignment mark is imaged by the first imaging unit. A second radiation unit radiates white light to an imaging area of a second imaging unit when the first alignment mark is imaged by the second imaging unit. A controller detects positions of the first alignment mark and the second alignment mark by processing images obtained by the first imaging unit and the second imaging unit, corrects the detected position of the first alignment mark based on a relationship between a wavelength and an intensity of reflection light reflected from the first substrate, and controls a moving unit based on the corrected position of the first alignment mark.

公开(公告)号：US20170110432A1

公开(公告)日：2017-04-20

申请号：US15290557

申请日：2016-10-11

Applicant: J-DEVICES CORPORATION

Inventor： Minoru KAI

IPC: H01L23/00 ,  H01L21/67 ,  H01L21/68

CPC classification number: H01L24/75 ,  H01L21/67132 ,  H01L21/67144 ,  H01L21/681 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/75312 ,  H01L2224/75316 ,  H01L2224/7532 ,  H01L2224/75702 ,  H01L2224/75745 ,  H01L2224/75753 ,  H01L2224/75822 ,  H01L2224/75824 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/8317 ,  H01L2224/8318 ,  H01L2224/83191 ,  H01L2924/00014 ,  H01L2924/0715 ,  H01L2924/0635 ,  H01L2924/06 ,  H01L2924/013 ,  H01L2924/00012

Abstract: A press fitting head comprising an elastic member in a part where the press fitting head contacts a semiconductor device, and an alignment mark recognition area capable of detecting an optically readable marker provided on a surface to be contacted to the semiconductor device is provided. Additionally, a semiconductor manufacturing apparatus in which the press fitting head is applied is provided.

公开(公告)号：US20160284566A1

公开(公告)日：2016-09-29

申请号：US15009969

申请日：2016-01-29

Applicant: FUJITSU LIMITED

Inventor： Hidehiko Kira ,  NORIO KAINUMA ,  TAKASHI KUBOTA ,  Takumi Masuyama

IPC: H01L21/52 ,  H01L21/56 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L23/544 ,  H01L23/3157 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/27334 ,  H01L2224/27436 ,  H01L2224/27632 ,  H01L2224/2783 ,  H01L2224/279 ,  H01L2224/29011 ,  H01L2224/29018 ,  H01L2224/29019 ,  H01L2224/29076 ,  H01L2224/29082 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/3201 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75301 ,  H01L2224/75745 ,  H01L2224/75753 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81207 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/273 ,  H01L21/78

Abstract: A first insulating film is applied onto a joining face of a semiconductor device including a connection terminal on a joining face, and the connection terminal is embedded inside the first insulating film. The second insulating film is formed on a joining target face of a joining target, which includes a connection target terminal on the joining target face, and the connection target terminal is embedded inside the second insulating film. The semiconductor device and the joining target are joined together by applying pressure and causing the semiconductor device and the joining target to make contact with each other.

Abstract translation: 第一绝缘膜被施加到包括接合面上的连接端子的半导体器件的接合面上，并且连接端子嵌入在第一绝缘膜的内部。 第二绝缘膜形成在接合对象的接合目标面上，该接合目标表面包括在接合目标面上的连接目标端子，并且连接目标端子嵌入第二绝缘膜内。 半导体器件和接合目标通过施加压力而接合在一起，并使半导体器件和接合目标彼此接触。

公开(公告)号：US09385104B2

公开(公告)日：2016-07-05

申请号：US14561572

申请日：2014-12-05

Applicant: Shinkawa Ltd.

Inventor： Daisuke Tani ,  Koichi Takahashi

IPC: G05G15/00 ,  H01L23/00 ,  H01L23/544 ,  B32B37/00 ,  B32B41/00 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L24/75 ,  B32B37/0046 ,  B32B41/00 ,  B32B2309/72 ,  B32B2313/00 ,  B32B2457/14 ,  H01L23/481 ,  H01L23/544 ,  H01L24/81 ,  H01L24/83 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/13101 ,  H01L2224/16145 ,  H01L2224/32146 ,  H01L2224/75753 ,  H01L2224/75754 ,  H01L2224/75901 ,  H01L2224/8113 ,  H01L2224/81815 ,  H01L2224/81908 ,  H01L2224/83123 ,  H01L2224/83129 ,  H01L2224/8313 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Provided is a flip-chip bonding apparatus (500) capable of stacking and bonding a second-layer of the semiconductor chip (30) onto a first-layer of the semiconductor chip (20) having first through-silicon vias, the second-layer of the semiconductor chip (30) having second through-silicon vias at positions corresponding to the first through-silicon vias. The flip-chip bonding apparatus (500) includes: a double-view camera (16) configured to take images of thechips (20) and (30); and a control unit (50) having a relative-position detection program (53) for detecting relative positions of the first-layer of the semiconductor chip (20) and the second-layer of the semiconductor chip (30) that are stacked and bonded based on an image of the first through-silicon vias on a surface of the first-layer of the semiconductor chip (20) taken by the double-view camera (16) before stacked bonding, and an image of the second through-silicon vias on a surface of the second-layer of the semiconductor chip (30) taken by the double-view camera (16) after stacked bonding. This provides accurate connection between through-silicon vias using a simple method.

Abstract translation: 提供了一种倒装芯片接合装置（500），其能够将半导体芯片（30）的第二层叠层并接合到具有第一穿硅通孔的半导体芯片（20）的第一层上，第二层 的半导体芯片（30）在对应于第一穿通硅通孔的位置处具有第二穿硅通孔。 倒装芯片接合装置（500）包括：被配置为拍摄芯片（20）和（30）的图像的双视图相机（16）。 以及具有相对位置检测程序（53）的控制单元（50），用于检测半导体芯片（20）的第一层和半导体芯片（30）的第二层的层叠和结合的相对位置 基于在层叠结合之前由双视摄像机（16）取得的半导体芯片（20）的第一层的表面上的第一穿硅通孔的图像，以及第二穿硅通孔的图像 在层叠接合之后，由双视摄影机（16）拍摄的半导体芯片（30）的第二层的表面上。 这通过简单的方法提供了硅通孔之间的准确连接。

公开(公告)号：US09330946B1

公开(公告)日：2016-05-03

申请号：US14946904

申请日：2015-11-20

Applicant: International Business Machines Corporation

Inventor： Mukta G. Farooq ,  Michael A. Gaynes ,  Katsuyuki Sakuma

IPC: H01L21/56 ,  H01L23/544 ,  H01L21/78 ,  H01L23/29 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/563 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/98 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/27013 ,  H01L2224/2919 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/29387 ,  H01L2224/2949 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81191 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/8388 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2924/0665 ,  H01L2924/351 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Structures and processes for die stacking using an opaque or translucent pre-applied underfill material generally include selectively applying a low surface tension material to at least a portion of an alignment mark surface on a die; and applying the opaque or translucent underfill material to the die surface, wherein the underfill material does not wet or adhere to the low surface tension material such that the alignment mark surface is free of underfill material.

Abstract translation: 使用不透明或半透明的预先施加的底部填充材料的模具堆叠的结构和工艺通常包括选择性地将低表面张力材料施加到模具上的对准标记表面的至少一部分上; 以及将不透明或半透明的底部填充材料施加到模具表面，其中底部填充材料不会湿润或粘附到低表面张力材料上，使得对准标记表面没有底部填充材料。

公开(公告)号：US20150108615A1

公开(公告)日：2015-04-23

申请号：US14059302

申请日：2013-10-21

Applicant: Oracle International Corporation

Inventor： Michael H. S. Dayringer ,  R. David Hopkins ,  Alex Chow

IPC: H01L25/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/72 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/16135 ,  H01L2224/16151 ,  H01L2224/1703 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/32145 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73257 ,  H01L2224/75705 ,  H01L2224/7598 ,  H01L2224/81007 ,  H01L2224/81129 ,  H01L2224/81141 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2224/81898 ,  H01L2224/819 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83136 ,  H01L2224/83193 ,  H01L2224/8385 ,  H01L2224/92143 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/37001

Abstract: An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terrace at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a pair of stepped terraces that approximately mirror the stepped terrace of the chip package and which provide vertical position references for an assembly tool that positions the set of semiconductor dies in the vertical stack during assembly of the chip package.

Abstract translation: 描述了使用组装部件组装芯片封装的组装部件和技术。 该芯片封装包括沿垂直方向布置成堆叠的一组半导体管芯，它们在水平方向彼此偏移以在垂直堆叠的一侧限定阶梯式台阶。 此外，可以使用组件部件组装芯片封装。 特别地，组装部件可以包括一对阶梯式台阶，其大致镜像芯片封装的阶梯式台阶，并且为组装工具提供垂直位置参考，该组装工具在组装芯片封装期间将该组半导体管芯定位在垂直堆叠中 。

公开(公告)号：US20140357025A1

公开(公告)日：2014-12-04

申请号：US14462776

申请日：2014-08-19

Applicant: Sony Corporation

Inventor： Satoru Wakiyama

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/544

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11015 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/14131 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/26135 ,  H01L2224/26145 ,  H01L2224/26165 ,  H01L2224/27334 ,  H01L2224/27416 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48 ,  H01L2224/73104 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/81903 ,  H01L2224/83007 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83141 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device including a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.

Abstract translation: 一种包括半导体元件的半导体器件; 形成在半导体元件上的焊盘电极; 形成在半导体元件上的对准标记; 形成在焊盘电极上的连接电极; 以及形成为覆盖连接电极的底部填充树脂。 来自半导体元件的对准标记的高度大于连接电极的高度。

公开(公告)号：US08653639B2

公开(公告)日：2014-02-18

申请号：US13156808

申请日：2011-06-09

Applicant: Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

Inventor： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

IPC: H01L21/02

CPC classification number: H01L21/561 ,  H01L21/6835 ,  H01L22/22 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05013 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2512 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2224/25177 ,  H01L2224/2746 ,  H01L2224/29024 ,  H01L2224/29144 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/75101 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83986 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2225/1058 ,  H01L2924/07802 ,  H01L2924/3511 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/82 ,  H01L2224/0231 ,  H01L21/78 ,  H01L2224/81 ,  H01L2924/00

Abstract: A layered chip package includes a main body and wiring. The main body has a main part. The main part has a top surface and a bottom surface and includes a plurality of layer portions that are stacked. The wiring includes a plurality of lines passing through all the plurality of layer portions. Each layer portion includes a semiconductor chip and a plurality of electrodes. The semiconductor chip has a first surface, and a second surface opposite thereto. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. The plurality of layer portions include two or more pairs of first and second layer portions in each of which the first and second layer portions are arranged so that the first or second surfaces of the respective semiconductor chips face each other. The plurality of electrodes include a plurality of first connection parts and a plurality of second connection parts. In the first layer portion, the plurality of first connection parts are in contact with the plurality of lines. In the second layer portion, the plurality of second connection parts are in contact with the plurality of lines.

Abstract translation: 分层芯片封装包括主体和布线。 主体有一个主要部分。 主要部分具有顶表面和底表面，并且包括堆叠的多个层部分。 布线包括穿过所有多个层部分的多条线。 各层部分包括半导体芯片和多个电极。 半导体芯片具有第一表面和与其相对的第二表面。 多个电极设置在半导体芯片的第一表面的一侧。 多个层部分包括两对或更多对第一和第二层部分，其中每个第一和第二层部分中的第一和第二层部分被布置成使得各个半导体芯片的第一或第二表面彼此面对。 多个电极包括多个第一连接部和多个第二连接部。 在第一层部分中，多个第一连接部分与多条线接触。 在第二层部分中，多个第二连接部分与多条线接触。