公开(公告)号：US09941240B2

公开(公告)日：2018-04-10

申请号：US13934982

申请日：2013-07-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ming-Kai Liu ,  Chun-Lin Lu ,  Kai-Chiang Wu ,  Shih-Wei Liang ,  Ching-Feng Yang ,  Yen-Ping Wang ,  Chia-Chun Miao

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/06152 ,  H01L2224/06179 ,  H01L2224/13005 ,  H01L2224/13028 ,  H01L2224/13116 ,  H01L2224/1403 ,  H01L2224/14152 ,  H01L2224/14179 ,  H01L2224/14515 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16105 ,  H01L2224/16106 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17104 ,  H01L2224/17515 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2924/0105 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/207 ,  H01L2924/00

Abstract: A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad. A method of forming a surface mounting component or a chip scale package assembly wherein the component or assembly has at least two different types of solder bumps.

公开(公告)号：US20180060479A1

公开(公告)日：2018-03-01

申请号：US15250934

申请日：2016-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lo ,  Chin-Chou Liu ,  Kuo-Nan Yang ,  Yu-Jen Chang

IPC: G06F17/50 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  G06F2217/40 ,  G06F2217/82 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/1411 ,  H01L2224/14515 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2224/29099

Abstract: An integrated fan-out package and a layout method thereof are provided. One integrated fan-out package includes a die and a fan-out substrate. The die has an interconnect structure therein. The fan-out substrate has a redistribution layer structure therein and a plurality of first conductive bumps on a first surface thereof. The first conductive bumps are in physical contact with an interconnect layer of the interconnect structure and a redistribution layer of the redistribution layer structure, and an aspect ratio of the first conductive bumps ranges from about 1/3 to 1/10.

公开(公告)号：US09646954B2

公开(公告)日：2017-05-09

申请号：US13085745

申请日：2011-04-13

Applicant: Shih-Wei Liang ,  Yu-Wen Liu ,  Hsien-Wei Chen

Inventor： Shih-Wei Liang ,  Yu-Wen Liu ,  Hsien-Wei Chen

IPC: H01L23/58 ,  H01L29/10 ,  H01L25/065 ,  H01L21/66 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L22/34 ,  H01L23/522 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05096 ,  H01L2224/05572 ,  H01L2224/14131 ,  H01L2224/14179 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: An integrated circuit system comprising a first integrated and at least one of a second integrated circuit, interposer or printed circuit board. The first integrated circuit further comprising a wiring stack, bond pads electrically connected to the wiring stack, and bump balls formed on the bond pads. First portions of the wiring stack and the bond pads form a functional circuit, and second portions of the wiring stack and the bond pads form a test circuit. A portion of the bump balls comprising dummy bump balls. The dummy bump balls electrically connected to the second portions of the wiring stack and the bond pads. The at least one of the second integrated circuit, interposer or printed circuit board forming a portion of the test circuit.

公开(公告)号：US09589921B2

公开(公告)日：2017-03-07

申请号：US14773817

申请日：2014-03-10

Applicant: PS4 Luxco S.a.r.l. ,  Mitsuaki Katagiri ,  Yu Hasegawa ,  Satoshi Isa

Inventor： Mitsuaki Katagiri ,  Yu Hasegawa ,  Satoshi Isa

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L23/12 ,  H01L21/56 ,  H01L21/66 ,  H05K1/02 ,  H05K1/14 ,  H05K1/18

CPC classification number: H01L24/17 ,  H01L21/561 ,  H01L22/32 ,  H01L23/12 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05025 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1411 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14181 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/83862 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/025 ,  H05K1/141 ,  H05K1/185 ,  H05K2201/10734 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00

Abstract: In one semiconductor device, a semiconductor chip has first and second pad electrodes disposed on the main surface thereof, insulating films that cover the main surface of the semiconductor chip, a rewiring layer that is disposed between the insulating films, and a plurality of external terminals disposed on the top of the insulating film. The plane size of the first pad electrode and the second pad electrode differ from one another, and the first pad electrode and the second pad electrode are connected to any of the plurality of external terminals via the rewiring layer.

Abstract translation: 在一个半导体器件中，半导体芯片具有设置在其主表面上的第一和第二焊盘电极，覆盖半导体芯片的主表面的绝缘膜，布置在绝缘膜之间的再布线层和多​​个外部端子 设置在绝缘膜的顶部。 第一焊盘电极和第二焊盘电极的平面尺寸彼此不同，并且第一焊盘电极和第二焊盘电极经由重新布线层连接到多个外部端子中的任何一个。

公开(公告)号：US20160155724A1

公开(公告)日：2016-06-02

申请号：US14955124

申请日：2015-12-01

Applicant: Taeyeong Kim ,  Byung Lyul Park ,  Seokho Kim ,  Pil-Kyu Kang ,  Hyoju Kim ,  Jin Ho An ,  Joo Hee Jang

Inventor： Taeyeong Kim ,  Byung Lyul Park ,  Seokho Kim ,  Pil-Kyu Kang ,  Hyoju Kim ,  Jin Ho An ,  Joo Hee Jang

IPC: H01L25/065 ,  H01L21/66 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L25/0657 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L22/32 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2224/03002 ,  H01L2224/03616 ,  H01L2224/0392 ,  H01L2224/04 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08146 ,  H01L2224/09181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14515 ,  H01L2224/16146 ,  H01L2224/73251 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80907 ,  H01L2224/92 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06596 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/80 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2924/00012 ,  H01L22/00 ,  H01L21/304 ,  H01L2221/68304 ,  H01L2221/68381 ,  H01L21/78

Abstract: Semiconductor devices having stacked structures and methods for fabricating the same are provided. A semiconductor device includes at least one single block including a first semiconductor chip and a second semiconductor chip stacked thereon. Each of the first and second semiconductor chips includes a semiconductor substrate including a through-electrode, a circuit layer on a front surface of the semiconductor substrate, and a front pad that is provided in the circuit layer and is electrically connected to the through-electrode. The surfaces of the semiconductor substrates face each other. The circuit layers directly contact each other such that the semiconductor chips are bonded to each other.

Abstract translation: 提供具有堆叠结构的半导体器件及其制造方法。 半导体器件包括至少一个单块，其包括堆叠在其上的第一半导体芯片和第二半导体芯片。 第一和第二半导体芯片中的每一个包括半导体衬底，该半导体衬底包括通孔，半导体衬底的前表面上的电路层和设置在电路层中并且与通孔电连接的前衬垫 。 半导体基板的表面彼此面对。 电路层彼此直接接触，使得半导体芯片彼此结合。

公开(公告)号：US09318454B2

公开(公告)日：2016-04-19

申请号：US14433711

申请日：2013-10-07

Applicant: Sharp Kabushiki Kaisha

Inventor： Takashi Matsui ,  Takeshi Horiguchi ,  Motoji Shiota

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  G02F1/1345 ,  H01L23/498

CPC classification number: H01L24/06 ,  G02F1/13452 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06131 ,  H01L2224/06133 ,  H01L2224/06135 ,  H01L2224/06177 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14177 ,  H01L2224/14515 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/81139 ,  H01L2224/81203 ,  H01L2224/8185 ,  H01L2224/83139 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2924/12041 ,  H01L2924/3511 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/00

Abstract: This drive chip has a configuration that is provided with: a base main body; two terminal groups that are respectively disposed along the base main body sides in the longitudinal direction of the base main body, said sides facing each other; a narrow-pitch section in one terminal group wherein terminals are disposed in a zigzag manner in two or more rows, said narrow-pitch section having a narrow terminal pitch in the longitudinal direction; a rough pitch section in the one terminal group, said rough pitch section having a terminal pitch in the longitudinal direction wider than that of the narrow pitch section; and a dummy bump that is disposed between the two terminal groups, said dummy bump being disposed parallel to the rough pitch section.

Abstract translation: 该驱动芯片具有以下结构：基部主体; 两个端子组，其分别沿着基底主体的基部主体侧设置在基部主体的纵向方向上，所述侧面彼此相对; 一个端子组中的窄节段，其中端子以锯齿形的方式设置成两行或多列，所述窄节段部分在纵向方向上具有窄的端子间距; 在一个端子组中的粗略俯仰部分，所述粗略俯仰部分的纵向方向上的端子间距比窄节段部分的端部间距宽; 以及设置在所述两个端子组之间的虚设凸块，所述虚设凸块平行于所述粗螺距部分设置。

公开(公告)号：US08965712B2

公开(公告)日：2015-02-24

申请号：US13051881

申请日：2011-03-18

Applicant: Takahiro Omori ,  Kenji Hirohata ,  Tomoko Monda ,  Katsuaki Hiraoka ,  Minoru Mukai

Inventor： Takahiro Omori ,  Kenji Hirohata ,  Tomoko Monda ,  Katsuaki Hiraoka ,  Minoru Mukai

IPC: G01B3/44 ,  B23K31/12 ,  B23K1/00 ,  H01L23/00 ,  G06F11/30 ,  G01R31/04 ,  H05K1/02 ,  H05K3/34

CPC classification number: B23K31/125 ,  B23K1/00 ,  G01N2203/0073 ,  G01N2203/0212 ,  G01R31/048 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/131 ,  H01L2224/14515 ,  H01L2224/14517 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2924/10253 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K3/3436 ,  H01L2924/014 ,  H01L2924/00

Abstract: A life predicting method for a solder joint includes a step of referring to a temperature history of a measurement object having a solder joint, a step of examining at least one physical quantity selected from the group consisting of amplitude, a cycle number, a mean temperature, and a periodic length of a temperature variation with a cycle count method from the temperature history, a step of calculating a strain range by utilizing a previously prepared response surface from the physical quantity examined with the cycle count method, and a step of calculating a strain range increasing rate from a strain range with reference to a previously obtained damage index and a strain variation history of the strain range.

Abstract translation: 用于焊点的寿命预测方法包括参考具有焊接接头的测量对象的温度历史的步骤，检查从由振幅，周期数，平均温度等组成的组中选择的至少一个物理量的步骤 以及来自温度历史的循环计数法的温度变化的周期长度，通过利用由循环计数法检查的物理量利用预先准备好的响应面来计算应变范围的步骤，以及计算 从应变范围的应变范围增加率参考先前获得的损伤指数和应变范围的应变变化历史。

公开(公告)号：US20140357025A1

公开(公告)日：2014-12-04

申请号：US14462776

申请日：2014-08-19

Applicant: Sony Corporation

Inventor： Satoru Wakiyama

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/544

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11015 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/14131 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/26135 ,  H01L2224/26145 ,  H01L2224/26165 ,  H01L2224/27334 ,  H01L2224/27416 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48 ,  H01L2224/73104 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/81903 ,  H01L2224/83007 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83141 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device including a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.

Abstract translation: 一种包括半导体元件的半导体器件; 形成在半导体元件上的焊盘电极; 形成在半导体元件上的对准标记; 形成在焊盘电极上的连接电极; 以及形成为覆盖连接电极的底部填充树脂。 来自半导体元件的对准标记的高度大于连接电极的高度。

公开(公告)号：US20140284749A1

公开(公告)日：2014-09-25

申请号：US14297779

申请日：2014-06-06

Applicant: Sony Corporation

Inventor： Satoru Wakiyama ,  Hiroshi Ozaki

IPC: H01L23/31 ,  H01L27/146 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L27/14636 ,  H01L21/56 ,  H01L21/563 ,  H01L23/31 ,  H01L24/05 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L27/14605 ,  H01L27/14609 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14634 ,  H01L27/14683 ,  H01L27/1469 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/29011 ,  H01L2224/29035 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83051 ,  H01L2224/83104 ,  H01L2224/83365 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15788 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Disclosed herein is a semiconductor device including: a first semiconductor chip having an electronic circuit section and a first connecting section formed on one surface thereof; a second semiconductor chip having a second connecting section formed on one surface thereof, the second semiconductor chip being mounted on the first semiconductor chip with the first and the second connecting sections connected to each other by a bump; a dam formed to fill a gap between the first and the second semiconductor chips on a part of an outer edge of the second semiconductor chip, the part of the outer edge being on a side of a region of formation of the electronic circuit section; and an underfill resin layer filled into the gap, protrusion of the resin layer from the outer edge of the second semiconductor chip to a side of the electronic circuit section being prevented by the dam.

Abstract translation: 本发明公开了一种半导体器件，包括：具有电子电路部分的第一半导体芯片和在其一个表面上形成的第一连接部分; 具有在其一个表面上形成的第二连接部分的第二半导体芯片，所述第二半导体芯片安装在所述第一半导体芯片上，所述第一和第二连接部分通过凸块相互连接; 形成为在所述第二半导体芯片的外缘的一部分上填充所述第一和第二半导体芯片之间的间隙的坝，所述外边缘的一部分位于所述电子电路部的形成区域的一侧; 并且填充到间隙中的底部填充树脂层，树脂层从第二半导体芯片的外边缘突出到电子电路部分的侧面被大坝阻止。

公开(公告)号：US08759210B2

公开(公告)日：2014-06-24

申请号：US13552788

申请日：2012-07-19

Applicant: Charles L. Arvin ,  Wolfgang Sauter ,  Jennifer D. Schuler

Inventor： Charles L. Arvin ,  Wolfgang Sauter ,  Jennifer D. Schuler

IPC: H01L21/44

CPC classification number: H01L24/14 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03614 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/14131 ,  H01L2224/14505 ,  H01L2224/14515 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/01029

Abstract: A solder structure for joining an IC chip to a package substrate, and method of forming the same are disclosed. In an embodiment, a structure is formed which includes a wafer having a plurality of solder structures disposed above the wafer. A ball limiting metallurgy (BLM) layer disposed beneath each of the solder structures, above the wafer. At least one of the plurality of solder structures has a first composition, and at least another of the plurality of solder structures has a second composition.

Abstract translation: 公开了一种用于将IC芯片连接到封装基板的焊料结构及其形成方法。 在一个实施例中，形成一种结构，其包括具有设置在晶片上方的多个焊料结构的晶片。 设置在晶片之上的焊料结构之下的球限制冶金（BLM）层。 所述多个焊料结构中的至少一个具有第一组成，并且所述多个焊料结构中的至少另一个具有第二组成。