公开(公告)号：US20240282658A1

公开(公告)日：2024-08-22

申请号：US18169998

申请日：2023-02-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John Knickerbocker ,  Mukta Ghate Farooq ,  Keiji Matsumoto

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/367

CPC classification number: H01L23/3185 ,  H01L21/561 ,  H01L23/29 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/3675 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/95 ,  H01L2224/16225 ,  H01L2224/2732 ,  H01L2224/2741 ,  H01L2224/2745 ,  H01L2224/27462 ,  H01L2224/2783 ,  H01L2224/29083 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29181 ,  H01L2224/29186 ,  H01L2224/2919 ,  H01L2224/32153 ,  H01L2224/32221 ,  H01L2224/33183 ,  H01L2224/95 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/04953 ,  H01L2924/07025

Abstract: A semiconductor integrated circuit device includes a first back-end-of-line region coupled to a first side of a front-end-of-line region, a second back-end-of-line region coupled to a second side of the front-end-of-line region, and a thermally conducting solder at least partially surrounding a perimeter of the front-end-of-line region, the first back-end-of-line region and the second back-end-of-line region.

公开(公告)号：US09214443B2

公开(公告)日：2015-12-15

申请号：US14272468

申请日：2014-05-07

Applicant: LEXTAR ELECTRONICS CORPORATION

Inventor： Yi-Jyun Chen

IPC: H01L23/00

CPC classification number: H01L24/32 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/2745 ,  H01L2224/276 ,  H01L2224/2783 ,  H01L2224/29005 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/29016 ,  H01L2224/29023 ,  H01L2224/29076 ,  H01L2224/2908 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32054 ,  H01L2224/32056 ,  H01L2224/32113 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32502 ,  H01L2224/32506 ,  H01L2224/83805 ,  H01L2224/83815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The present invention provides a eutectic solder structure for a chip including a substrate and a solder structure on the substrate. The solder structure includes an alternate lamination of a plurality of first metal layers and a plurality of second metal layers, wherein each second metal layer has a continuous region and a plurality of openings and the melting point of the plurality of second metal layers is higher than that of the plurality of first metal layers. The eutectic solder structure for a chip also includes a chip on the solder structure, wherein the chip is bonded to the substrate by a eutectic reaction of the solder structure.

Abstract translation: 本发明提供了一种用于芯片的共晶焊料结构，其包括在基板上的基板和焊料结构。 焊料结构包括多个第一金属层和多个第二金属层的交替叠层，其中每个第二金属层具有连续区域和多个开口，并且多个第二金属层的熔点高于 多个第一金属层中的第一金属层。 用于芯片的共晶焊料结构还包括焊料结构上的芯片，其中芯片通过焊料结构的共晶反应结合到衬底。

公开(公告)号：US08324105B2

公开(公告)日：2012-12-04

申请号：US12855765

申请日：2010-08-13

Applicant: Jui-Hung Cheng

Inventor： Jui-Hung Cheng

IPC: H01L21/00

CPC classification number: H01L24/29 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/27416 ,  H01L2224/2783 ,  H01L2224/27831 ,  H01L2224/29015 ,  H01L2224/29019 ,  H01L2224/2919 ,  H01L2224/32055 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/8385 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00

Abstract: A stacking carrier and a stacking method are provided. The stacking method is used between a wafer and a stacking carrier having the same shape. The stacking method includes the following steps. Firstly, an adhesive layer is coated on a surface of the carrier. Then, the adhesive layer corresponding to an edge of the carrier is partially removed, thereby defining at least one adhesive layer indentation. Afterwards, the wafer is stacked on the carrier through the adhesive layer having the adhesive layer indentation.

Abstract translation: 提供堆叠载体和堆垛方法。 在具有相同形状的晶片和堆叠载体之间使用层叠方法。 堆叠方法包括以下步骤。 首先，在载体的表面上涂布粘合剂层。 然后，对应于载体边缘的粘合剂层被部分地去除，从而限定至少一个粘合剂层压痕。 之后，通过具有粘合剂层压痕的粘合剂层将晶片堆叠在载体上。

公开(公告)号：US20090275192A1

公开(公告)日：2009-11-05

申请号：US12502994

申请日：2009-07-14

Applicant: JURGEN H. DANIEL ,  ANA C. ARIAS

Inventor： JURGEN H. DANIEL ,  ANA C. ARIAS

IPC: H01L21/44

CPC classification number: H05K3/107 ,  B82Y10/00 ,  G03F7/0017 ,  H01L27/14683 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L2224/27001 ,  H01L2224/2783 ,  H01L2224/2784 ,  H01L2224/73104 ,  H05K3/0017 ,  H05K3/0023 ,  H05K2203/0278 ,  H05K2203/0582 ,  H01L2924/00012

Abstract: A method forms a first active electronic layer, prints an array of pillars on the first active electronic layer, dispenses a curable polymer over the array of pillars, molds the curable polymer by contacting the curable polymer with a mold structure to displace the curable polymer from upper surfaces of the pillars, cures the curable polymer to produce a hardened polymer, and removes the array of pillars to leave an array of holes in the hardened polymer. Another method provides a substrate having selected areas, prints an array of pillars on the substrate, dispenses a curable polymer over the array of pillars, molds the curable polymer by contacting the array of pillars with a mold structure to displace the curable polymer from upper surfaces of the pillars, cures the curable polymer to produce a hardened polymer, and removes the array of pillars to leave an array of holes in the hardened polymer corresponding to the selected areas. Another method forms a first active electronic layer on a substrate, prints an array of conductive pillars on the active electronic layer on a substrate, dispenses a curable polymer on the array of conductive pillars, molds the curable polymer by contacting the array of pillars with a mold structure to displace the curable polymer from the upper surfaces of the conductive pillars, curing the curable polymer to produce a hardened polymer, and forms a second active electronic layer on the hardened polymer such that the second active electronic layer is in electrical connection with the first active electronic layer through the conductive pillars.

Abstract translation: 一种方法形成第一活性电子层，在第一活性电子层上印刷柱状阵列，在柱阵列上分配可固化聚合物，通过使可固化聚合物与模具结构接触来模制可固化聚合物，以将可固化聚合物从 柱的上表面固化可固化聚合物以产生硬化的聚合物，并除去柱阵列，以在硬化的聚合物中留下孔阵列。 另一种方法提供了具有选定区域的基材，在基材上印刷柱状阵列，在柱阵列上分配可固化聚合物，通过将支柱阵列与模具结构接触来模制可固化聚合物，以将可固化聚合物从上表面 的柱子固化可固化聚合物以产生硬化的聚合物，并除去柱阵列，以在对应于选定区域的硬化聚合物中留下孔阵列。 另一种方法在衬底上形成第一有源电子层，在衬底上的有源电子层上印刷导电柱阵列，在导电柱阵列上分配可固化聚合物，通过将支柱阵列与 模制结构，以从导电柱的上表面置换可固化聚合物，固化可固化聚合物以产生硬化的聚合物，并在硬化的聚合物上形成第二有源电子层，使得第二有源电子层与 第一个有源电子层通过导电柱。

公开(公告)号：US20230260945A1

公开(公告)日：2023-08-17

申请号：US17672729

申请日：2022-02-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jiun-Yi Wu ,  Chen-Hua Yu ,  Yu-Min Liang ,  Jung-Wei Cheng

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L24/20 ,  H01L21/565 ,  H01L23/481 ,  H01L23/49822 ,  H01L24/73 ,  H01L24/32 ,  H01L24/24 ,  H01L24/19 ,  H01L24/27 ,  H01L2225/1058 ,  H01L2224/73267 ,  H01L2224/221 ,  H01L2224/32225 ,  H01L2224/32057 ,  H01L2224/24225 ,  H01L2224/2783 ,  H01L25/50

Abstract: A semiconductor structure includes a substrate component, an IC die component over the substrate component, and a composite redistribution structure interposed between and electrically coupled to the substrate and IC die components. The composite redistribution structure includes a local interconnect component between a first redistribution structure overlying the substrate component and a second redistribution structure underlying the IC die component, and an insulating encapsulation between the first and second redistribution structures and embedding the local interconnect component therein. The local interconnect component includes TSVs penetrating through a substrate and electrically coupled to first and second conductive connectors, the first conductive connectors between the first redistribution structure and a first side of the substrate, the second conductive connectors between the second redistribution structure and a second side of the substrate, and a first insulating layer between the first redistribution structure and the first side and laterally covering the first conductive connectors.

公开(公告)号：US11705425B2

公开(公告)日：2023-07-18

申请号：US17301843

申请日：2021-04-15

Applicant: Micron Technology, Inc.

Inventor： Benjamin L. McClain ,  Brandon P. Wirz ,  Zhaohui Ma

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L24/75 ,  H01L21/4853 ,  H01L21/563 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/13 ,  H01L24/16 ,  H01L24/94 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/27003 ,  H01L2224/2783 ,  H01L2224/2784 ,  H01L2224/27436 ,  H01L2224/32013 ,  H01L2224/32058 ,  H01L2224/32059 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/73103 ,  H01L2224/73204 ,  H01L2224/7532 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75303 ,  H01L2224/75312 ,  H01L2224/75318 ,  H01L2224/75745 ,  H01L2224/8182 ,  H01L2224/81169 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/83203 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2924/00012 ,  H01L2224/94 ,  H01L2224/27 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/9212 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/9211 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/81169 ,  H01L2924/00014 ,  H01L2224/2783 ,  H01L2924/00012

Abstract: A bond tip for thermocompression bonding a bottom surface includes a die contact area and a low surface energy material covering at least a portion of the bottom surface. The low surface energy material may cover substantially all of the bottom surface, or only a peripheral portion surrounding the die contact area. The die contact area may be recessed with respect to the peripheral portion a depth at least as great as a thickness of a semiconductor die to be received in the recessed die contact area. A method of thermocompression bonding is also disclosed.

公开(公告)号：US20170233615A1

公开(公告)日：2017-08-17

申请号：US15518680

申请日：2016-01-20

Applicant: SEKISUI CHEMICAL CO., LTD.

Inventor： Mitsuru Tanikawa ,  Takashi Watanabe ,  Yusuke Fujita ,  Yoshito Fujita ,  Tasuku Yamada

IPC: C09J9/02 ,  C09D11/101 ,  C09D11/107 ,  C09D133/14 ,  C09J5/04 ,  C09D11/52 ,  C09J133/14 ,  C09J133/10 ,  H01L23/00 ,  C09J5/06 ,  C09D11/30 ,  C09D133/10

CPC classification number: C09D133/14 ,  C08G59/4215 ,  C08G59/5033 ,  C08G59/686 ,  C08L33/08 ,  C09D11/101 ,  C09D11/107 ,  C09D11/30 ,  C09D11/52 ,  C09D133/10 ,  C09J4/06 ,  C09J5/04 ,  C09J5/06 ,  C09J9/02 ,  C09J133/10 ,  C09J133/14 ,  C09J163/00 ,  C09J171/12 ,  C09J201/02 ,  C09J2203/326 ,  C09J2205/114 ,  C09J2205/31 ,  C09J2433/00 ,  C09J2461/00 ,  C09J2463/00 ,  H01L21/52 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/91 ,  H01L2224/2741 ,  H01L2224/2783 ,  H01L2224/27848 ,  H01L2224/29083 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/83026 ,  H01L2224/8322 ,  H01L2224/83359 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/83947 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399 ,  C08L33/04

Abstract: Provided is an inkjet adhesive which is applied using an inkjet device, wherein the adhesive can suppress generation of voids in the adhesive layer and, after bonding, can enhance adhesiveness, moisture-resistant adhesion reliability, and cooling/heating cycle reliability. An inkjet adhesive according to the present invention comprises a photocurable compound, a photo-radical initiator, a thermosetting compound having one or more cyclic ether groups or cyclic thioether groups, and a compound capable of reacting with the thermosetting compound, and the compound capable of reacting with the thermosetting compound contains aromatic amine.

公开(公告)号：US20130049230A1

公开(公告)日：2013-02-28

申请号：US13664169

申请日：2012-10-30

Applicant: VICTORY GAIN GROUP CORPORATION

Inventor： Jui-Hung CHENG

IPC: H01L21/50 ,  H01L23/12

CPC classification number: H01L24/29 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/27416 ,  H01L2224/2783 ,  H01L2224/27831 ,  H01L2224/29015 ,  H01L2224/29019 ,  H01L2224/2919 ,  H01L2224/32055 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/8385 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00

Abstract: A stacking carrier and a stacking method are provided. The stacking method is used between a wafer and a stacking carrier having the same shape. The stacking method includes the following steps. Firstly, an adhesive layer is coated on a surface of the carrier. Then, the adhesive layer corresponding to an edge of the carrier is partially removed, thereby defining at least one adhesive layer indentation. Afterwards, the wafer is stacked on the carrier through the adhesive layer having the adhesive layer indentation.

Abstract translation: 提供堆叠载体和堆垛方法。 在具有相同形状的晶片和堆叠载体之间使用层叠方法。 堆叠方法包括以下步骤。 首先，在载体的表面上涂布粘合剂层。 然后，对应于载体边缘的粘合剂层被部分地去除，从而限定至少一个粘合剂层压痕。 之后，通过具有粘合剂层压痕的粘合剂层将晶片堆叠在载体上。

公开(公告)号：US20080150187A1

公开(公告)日：2008-06-26

申请号：US11615229

申请日：2006-12-22

Applicant: Jurgen H. Daniel ,  Ana C. Arias

Inventor： Jurgen H. Daniel ,  Ana C. Arias

IPC: C04B41/45

CPC classification number: H05K3/107 ,  B82Y10/00 ,  G03F7/0017 ,  H01L27/14683 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L2224/27001 ,  H01L2224/2783 ,  H01L2224/2784 ,  H01L2224/73104 ,  H05K3/0017 ,  H05K3/0023 ,  H05K2203/0278 ,  H05K2203/0582 ,  H01L2924/00012

Abstract: A method forms a first active electronic layer, prints an array of pillars on the first active electronic layer, dispenses a curable polymer over the array of pillars, molds the curable polymer by contacting the curable polymer with a mold structure to displace the curable polymer from upper surfaces of the pillars, cures the curable polymer to produce a hardened polymer, and removes the array of pillars to leave an array of holes in the hardened polymer. Another method provides a substrate having selected areas, prints an array of pillars on the substrate, dispenses a curable polymer over the array of pillars, molds the curable polymer by contacting the array of pillars with a mold structure to displace the curable polymer from upper surfaces of the pillars, cures the curable polymer to produce a hardened polymer, and removes the array of pillars to leave an array of holes in the hardened polymer corresponding to the selected areas. Another method forms a first active electronic layer on a substrate, prints an array of conductive pillars on the active electronic layer on a substrate, dispenses a curable polymer on the array of conductive pillars, molds the curable polymer by contacting the array of pillars with a mold structure to displace the curable polymer from the upper surfaces of the conductive pillars, curing the curable polymer to produce a hardened polymer, and forms a second active electronic layer on the hardened polymer such that the second active electronic layer is in electrical connection with the first active electronic layer through the conductive pillars.

Abstract translation: 一种方法形成第一活性电子层，在第一活性电子层上印刷柱状阵列，在柱阵列上分配可固化聚合物，通过使可固化聚合物与模具结构接触来模制可固化聚合物，以将可固化聚合物从 柱的上表面固化可固化聚合物以产生硬化的聚合物，并除去柱阵列，以在硬化的聚合物中留下孔阵列。 另一种方法提供了具有选定区域的基材，在基材上印刷柱状阵列，在柱阵列上分配可固化聚合物，通过将支柱阵列与模具结构接触来模制可固化聚合物，以将可固化聚合物从上表面 的柱子固化可固化聚合物以产生硬化的聚合物，并除去柱阵列，以在对应于选定区域的硬化聚合物中留下孔阵列。 另一种方法在衬底上形成第一有源电子层，在衬底上的有源电子层上印刷导电柱阵列，在导电柱阵列上分配可固化聚合物，通过将支柱阵列与 模制结构，以从导电柱的上表面置换可固化聚合物，固化可固化聚合物以产生硬化的聚合物，并在硬化的聚合物上形成第二有源电子层，使得第二有源电子层与 第一个有源电子层通过导电柱。

公开(公告)号：US12002773B2

公开(公告)日：2024-06-04

申请号：US17190850

申请日：2021-03-03

Applicant: Raytheon Company

Inventor： Andrew Clarke ,  Chad Fulk ,  Aaron M. Ramirez

IPC: H01L25/16 ,  H01L23/00 ,  H01L31/02 ,  H01L31/0216 ,  H01L31/0224 ,  H01L31/0296 ,  H01L31/09

CPC classification number: H01L24/05 ,  H01L24/08 ,  H01L24/29 ,  H01L24/32 ,  H01L25/167 ,  H01L31/02002 ,  H01L31/0216 ,  H01L24/03 ,  H01L24/27 ,  H01L24/83 ,  H01L31/0224 ,  H01L31/02966 ,  H01L31/09 ,  H01L2224/03845 ,  H01L2224/05017 ,  H01L2224/051 ,  H01L2224/05564 ,  H01L2224/05609 ,  H01L2224/0801 ,  H01L2224/08145 ,  H01L2224/2783 ,  H01L2224/29026 ,  H01L2224/29034 ,  H01L2224/29188 ,  H01L2224/32145 ,  H01L2224/80815 ,  H01L2224/83896 ,  H01L2924/3512

Abstract: An electrical device includes a substrate, an insulating layer supported by the substrate, and an electrically conductive vertical interconnect disposed in a via hole of the insulating layer. The insulating layer may be configured to provide a coefficient of thermal expansion (CTE) that is equal to or greater than a CTE of the vertical interconnect to thereby impart axial compressive forces at opposite ends of the interconnect. The vertical interconnect may be a hybrid interconnect structure including a low CTE conductor post having a pocket that contains a high CTE conductor contact. At low operating temperatures, the high CTE conductor contact is under tension due to the higher CTE, and thus the high CTE conductor contact relieves strain in the device by void expansion and elongation.