公开(公告)号：US12057430B2

公开(公告)日：2024-08-06

申请号：US17436331

申请日：2020-08-05

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jungyun Jo

IPC: H01L23/00 ,  H01L25/18 ,  H10K59/131

CPC classification number: H01L24/83 ,  H01L24/05 ,  H01L24/32 ,  H01L24/33 ,  H01L25/18 ,  H10K59/131 ,  H01L24/06 ,  H01L24/29 ,  H01L24/30 ,  H01L2224/04026 ,  H01L2224/05073 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05573 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/29013 ,  H01L2224/30131 ,  H01L2224/32014 ,  H01L2224/32105 ,  H01L2224/32145 ,  H01L2224/3303 ,  H01L2224/33106 ,  H01L2224/33517 ,  H01L2224/83205 ,  H01L2224/83862

Abstract: A display device includes a display substrate, a signal pad part, an insulating layer, a connection pad part, and an electronic component. The signal pad part includes first and second signal pad parts, which face each other in one direction. The insulating layer covers the signal pad part. The connection pad part is disposed on the insulating layer and includes a first connection pad part overlapping the first signal pad part and a second connection pad part. The second connection pad part is electrically connected to the first connection pad part and is in electrical contact with the second signal pad part through a contact hole defined in the insulating layer. The electronic component includes a bump that is in electrical contact with the first connection pad part. The first signal pad part includes a plurality of signal pad portions spaced apart from each other.

公开(公告)号：US12051670B2

公开(公告)日：2024-07-30

申请号：US17490224

申请日：2021-09-30

Applicant: Micron Technology, Inc.

Inventor： Mark E. Tuttle ,  John F. Kaeding ,  Owen R. Fay ,  Eiichi Nakano ,  Shijian Luo

IPC: H01L23/49 ,  H01L23/00

CPC classification number: H01L24/32 ,  H01L24/29 ,  H01L24/33 ,  H01L2224/29078 ,  H01L2224/32105 ,  H01L2224/3303 ,  H01L2224/33107 ,  H01L2224/3313 ,  H01L2924/381

Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate. The method may include passing electrical current through the plurality of interconnects.

公开(公告)号：US09941233B2

公开(公告)日：2018-04-10

申请号：US14789233

申请日：2015-07-01

Applicant: ROHM CO., LTD.

Inventor： Hiroaki Matsubara ,  Yasumasa Kasuya ,  Taro Nishioka

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/544 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48

CPC classification number: H01L24/32 ,  H01L21/4828 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/544 ,  H01L23/564 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05639 ,  H01L2224/06155 ,  H01L2224/29139 ,  H01L2224/29239 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/29387 ,  H01L2224/2939 ,  H01L2224/29499 ,  H01L2224/32013 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83439 ,  H01L2224/85439 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/05442 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/207

Abstract: An electronic device includes an electronic element, a plurality of first sub-electrodes arrayed in a first direction, a plurality of second sub-electrodes arrayed in a second direction that is orthogonal to the first direction, a dummy electrode, and a sealing resin. The sealing resin has a resin back surface from which the plurality of first sub-electrodes, the plurality of second sub-electrodes and the dummy electrode are exposed. The plurality of second sub-electrodes are located further in the first direction than any of the plurality of first sub-electrodes. The plurality of first sub-electrodes are located further in the second direction than any of the plurality of second sub-electrodes. The dummy electrode is located further in the first direction than any of the plurality of first sub-electrodes, and is located further in the second direction than any of the plurality of second sub-electrodes.

公开(公告)号：US09847235B2

公开(公告)日：2017-12-19

申请号：US14190952

申请日：2014-02-26

Applicant: Infineon Technologies AG

Inventor： Carsten von Koblinski ,  Ulrike Fastner ,  Andre Brockmeier ,  Peter Zorn

IPC: H01L21/52 ,  H01L21/78 ,  H01L21/683 ,  H01L23/00 ,  H01L23/051 ,  H01L23/492 ,  H01L23/498 ,  H01L21/48 ,  H01L23/367

CPC classification number: H01L21/52 ,  H01L21/4803 ,  H01L21/683 ,  H01L21/78 ,  H01L23/051 ,  H01L23/3677 ,  H01L23/492 ,  H01L23/49861 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0346 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2224/2732 ,  H01L2224/29011 ,  H01L2224/29188 ,  H01L2224/2919 ,  H01L2224/32105 ,  H01L2224/32111 ,  H01L2224/32155 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82105 ,  H01L2224/82947 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/9202 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/13055 ,  H01L2924/15156 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2224/19 ,  H01L2224/83

Abstract: A carrier substrate having a plurality of receptacles each for receiving and carrying a semiconductor chip is provided. Semiconductor chips are arranged in the receptacles, and metal is plated in the receptacles to form a metal structure on and in contact with the semiconductor chips. The carrier substrate is cut to form separate semiconductor devices.

公开(公告)号：US09818681B2

公开(公告)日：2017-11-14

申请号：US14969555

申请日：2015-12-15

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Yoshihiro Machida

IPC: H05K1/18 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H05K3/46 ,  H05K7/00

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06183 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16014 ,  H01L2224/16105 ,  H01L2224/16106 ,  H01L2224/16175 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32175 ,  H01L2224/32227 ,  H01L2224/33183 ,  H01L2224/73253 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83101 ,  H01L2224/83424 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83815 ,  H01L2924/15311 ,  H05K1/185 ,  H05K3/4614 ,  H05K2201/10303 ,  H05K2203/061 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2224/05144

Abstract: A wiring substrate includes a first substrate and an electronic component mounted on an upper surface of the first substrate. A first pad is formed on an uppermost wiring layer of the first substrate. A connection terminal is formed on the electronic component and is located proximate to the first pad in a plan view. The wiring substrate further includes a connection member formed on the first pad to electrically connect the first pad and the connection terminal. The connection member includes a rod-shaped core and a solder layer, which is coated around the core and joined to the first pad. The solder layer includes a bulge that spreads from the core of the connection member in a planar direction. The bulge is joined to the connection terminal of the electronic component.

公开(公告)号：US09716060B2

公开(公告)日：2017-07-25

申请号：US14692769

申请日：2015-04-22

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Chao Chiu ,  Chun-Hsien Lin ,  Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H05K3/00 ,  H05K3/32 ,  H05K1/18 ,  H01L23/538 ,  H01L23/00 ,  H05K1/02 ,  H05K3/10 ,  H05K3/46 ,  H01L23/31 ,  H01L21/683

CPC classification number: H01L23/49838 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/189 ,  H05K3/0026 ,  H05K3/007 ,  H05K3/108 ,  H05K3/32 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665

Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.

公开(公告)号：US20170069595A1

公开(公告)日：2017-03-09

申请号：US15257427

申请日：2016-09-06

Applicant: Invensas Corporation

Inventor： Belgacem Haba

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05687 ,  H01L2224/113 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13193 ,  H01L2224/1403 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/16146 ,  H01L2224/271 ,  H01L2224/2733 ,  H01L2224/2741 ,  H01L2224/27436 ,  H01L2224/27849 ,  H01L2224/29027 ,  H01L2224/29028 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29393 ,  H01L2224/29499 ,  H01L2224/3201 ,  H01L2224/32105 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75102 ,  H01L2224/8109 ,  H01L2224/81101 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8309 ,  H01L2224/83101 ,  H01L2224/83143 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/8388 ,  H01L2224/9211 ,  H01L2224/9212 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/381 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/0675 ,  H01L2924/0635 ,  H01L2924/00012 ,  H01L2924/069 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/27

Abstract: 3D joining of microelectronic components and a conductively self-adjusting anisotropic matrix are provided. In an implementation, an adhesive matrix automatically makes electrical connections between two surfaces that have electrical contacts, and bonds the two surfaces together. Conductive members in the adhesive matrix are aligned to automatically establish electrical connections between at least partially aligned contacts on each of the two surfaces while providing nonconductive adhesion between parts of the two surfaces lacking aligned contacts. An example method includes forming an adhesive matrix between two surfaces to be joined, including conductive members anisotropically aligned in an adhesive medium, then pressing the two surfaces together to automatically connect corresponding electrical contacts that are at least partially aligned on the two surfaces. The adhesive medium in the matrix secures the two surfaces together.

Abstract translation: 提供了微电子部件的3D连接和导电自调节各向异性矩阵。 在一个实施方案中，粘合剂基质自动地在具有电接触的两个表面之间进行电连接，并将两个表面粘合在一起。 粘合剂基体中的导电构件对准以在两个表面中的每一个上的至少部分对准的触点之间自动建立电连接，同时在缺少对准的触点的两个表面的部分之间提供非导电粘附。 一个示例性方法包括在待接合的两个表面之间形成粘合剂基体，包括在粘合剂介质中各向异性排列的导电构件，然后将两个表面压在一起，以自动连接在两个表面上至少部分对准的对应的电触头。 基体中的粘合剂介质将两个表面固定在一起。

公开(公告)号：US20160351466A1

公开(公告)日：2016-12-01

申请号：US15221543

申请日：2016-07-27

Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.

Inventor： Nathan Perkins

IPC: H01L23/367 ,  H01L23/498

CPC classification number: H01L23/367 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/4821 ,  H01L23/49844 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/32 ,  H01L24/48 ,  H01L29/0657 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/04026 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32225 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/142 ,  H01L2924/1421 ,  H01L2224/45099

Abstract: A semiconductor structure includes a semiconductor substrate having a recess disposed beneath a semiconductor device. The semiconductor structure also includes a thermally conductive core disposed in the recess, and a package substrate including a heat sink. The heat sink is in thermal contact with the thermally conductive core.

公开(公告)号：US09472484B2

公开(公告)日：2016-10-18

申请号：US14624526

申请日：2015-02-17

Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.

Inventor： Nathan Perkins

IPC: H01L23/34 ,  H01L23/367

CPC classification number: H01L23/367 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/4821 ,  H01L23/49844 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/32 ,  H01L24/48 ,  H01L29/0657 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/04026 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32225 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/142 ,  H01L2924/1421 ,  H01L2224/45099

Abstract: A semiconductor structure includes a semiconductor substrate having a recess disposed beneath a semiconductor device. The semiconductor structure also includes a thermally conductive core disposed in the recess, and a package substrate including a heat sink. The heat sink is in thermal contact with the thermally conductive core.

Abstract translation: 半导体结构包括具有设置在半导体器件下方的凹部的半导体衬底。 半导体结构还包括设置在凹部中的导热芯，以及包括散热器的封装基板。 散热片与导热芯热接触。

公开(公告)号：US20160190053A1

公开(公告)日：2016-06-30

申请号：US14969555

申请日：2015-12-15

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Yoshihiro MACHIDA

IPC: H01L23/498 ,  H05K1/18 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06183 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16014 ,  H01L2224/16105 ,  H01L2224/16106 ,  H01L2224/16175 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32175 ,  H01L2224/32227 ,  H01L2224/33183 ,  H01L2224/73253 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83101 ,  H01L2224/83424 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83815 ,  H01L2924/15311 ,  H05K1/185 ,  H05K3/4614 ,  H05K2201/10303 ,  H05K2203/061 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2224/05144

Abstract: A wiring substrate includes a first substrate and an electronic component mounted on an upper surface of the first substrate. A first pad is formed on an uppermost wiring layer of the first substrate. A connection terminal is formed on the electronic component and is located proximate to the first pad in a plan view. The wiring substrate further includes a connection member formed on the first pad to electrically connect the first pad and the connection terminal. The connection member includes a rod-shaped core and a solder layer, which is coated around the core and joined to the first pad. The solder layer includes a bulge that spreads from the core of the connection member in a planar direction. The bulge is joined to the connection terminal of the electronic component.

Abstract translation: 布线基板包括第一基板和安装在第一基板的上表面上的电子部件。 第一衬垫形成在第一衬底的最上布线层上。 连接端子形成在电子部件上并且在俯视图中位于第一焊盘附近。 布线基板还包括形成在第一焊盘上的电连接第一焊盘和连接端子的连接部件。 连接构件包括棒状芯和焊料层，其被涂覆在芯周围并且连接到第一焊盘。 焊料层包括在平面方向上从连接构件的芯部扩散的凸起。 凸起连接到电子部件的连接端子。