公开(公告)号：US08168527B2

公开(公告)日：2012-05-01

申请号：US12534885

申请日：2009-08-04

Applicant: Mou-Shiung Lin ,  Chiu-Ming Chou

Inventor： Mou-Shiung Lin ,  Chiu-Ming Chou

IPC: H01L21/768

CPC classification number: H01L21/563 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/86 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05166 ,  H01L2224/05553 ,  H01L2224/05568 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/13023 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/13583 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13669 ,  H01L2224/13673 ,  H01L2224/13676 ,  H01L2224/13683 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48673 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48769 ,  H01L2224/48773 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/48873 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06586 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/48869 ,  H01L2224/48744 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A semiconductor chip includes a silicon substrate, a first dielectric layer over said silicon substrate, a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said metallization structure and over said first and second dielectric layers, an opening in said passivation layer exposing a pad of said metallization structure, a polymer bump over said passivation layer, wherein said polymer bump has a thickness of between 5 and 25 micrometers, an adhesion/barrier layer on said pad exposed by said opening, over said passivation layer and on a top surface and a portion of sidewall(s) of said polymer bump, a seed layer on said adhesion/barrier layer; and a third metal layer on said seed layer.

Abstract translation: 半导体芯片包括硅衬底，在所述硅衬底上的第一电介质层，在所述第一介电层上的金属化结构，其中所述金属化结构包括在所述第一金属层上的第一金属层和第二金属层，第二介电层 在所述第一和第二金属层之间的钝化层，在所述金属化结构之上并且在所述第一和第二介电层上方的钝化层，所述钝化层中的开口暴露所述金属化结构的焊盘，所述钝化层上的聚合物凸块，其中所述聚合物凸块 具有5至25微米的厚度，所述焊盘上的粘附/阻挡层，由所述开口暴露在所述钝化层上，所述聚合物凸块的顶表面和侧壁的一部分上，所述 粘合/阻隔层; 以及所述籽晶层上的第三金属层。

公开(公告)号：US07855137B2

公开(公告)日：2010-12-21

申请号：US12190173

申请日：2008-08-12

Applicant: Mukta G. Farooq ,  Waldemar Walter Kocon ,  Kevin Shawn Petrarca ,  Richard Paul Volant

Inventor： Mukta G. Farooq ,  Waldemar Walter Kocon ,  Kevin Shawn Petrarca ,  Richard Paul Volant

IPC: H01L21/4763 ,  H01L21/44

CPC classification number: H01L24/11 ,  H01L21/76852 ,  H01L21/76885 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/13083 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13671 ,  H01L2224/13673 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/01015 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05099

Abstract: A method of forming conductive pillars on a semiconductor wafer in which the conductive pillars are plated with a protecting coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP. Only the side of the conductive pillars are plated. The ends of the conductive pillars are free of the protective plating so that the conductive pillars can be readily joined to the pads of a packaging substrate. Also disclosed is a sidewall-protected conductive pillar having a protective coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP thereon.

Abstract translation: 在半导体晶片上形成导电柱的方法，其中导电柱镀有Ni，Co，Cr，Rh，NiP，NiB，CoWP或CoP的保护涂层。 只有导电柱的一面被电镀。 导电柱的端部没有保护电镀，使得导电柱可以容易地接合到封装基板的焊盘。 还公开了一种侧壁保护的导电柱，其上具有Ni，Co，Cr，Rh，NiP，NiB，CoWP或CoP的保护涂层。

公开(公告)号：US20160093581A1

公开(公告)日：2016-03-31

申请号：US14957115

申请日：2015-12-02

Applicant: SK hynix Inc.

Inventor： Rae Hyung JEONG ,  Hyun Kyu RYU

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05557 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05673 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/10126 ,  H01L2224/11002 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11845 ,  H01L2224/119 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13673 ,  H01L2224/14051 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L21/304 ,  H01L21/56 ,  H01L2224/034 ,  H01L2224/114 ,  H01L2224/1184 ,  H01L2224/03612

Abstract: A semiconductor device includes a through electrode penetrating a substrate such that a first end portion of the through electrode protrudes from a first surface of the substrate, a passivation layer covering the first surface of the substrate and a sidewall of the first end portion of the through electrode, a bump having a lower portion penetrating the passivation layer and coupled to the first end portion of the through electrode, and a lower metal layer disposed between the bump and the first end portion of the through electrode. The lower metal layer extends onto a sidewall of the bump and has a concave shape.

Abstract translation: 一种半导体器件包括穿透基片的通孔，使得通孔的第一端部从基板的第一表面突出，覆盖基板的第一表面的钝化层和通孔的第一端部的侧壁 电极，具有穿透钝化层的下部并且连接到通孔的第一端部的凸块以及设置在凸块与通孔的第一端部之间的下金属层。 下部金属层延伸到凸块的侧壁上并具有凹形。

公开(公告)号：US20150179545A1

公开(公告)日：2015-06-25

申请号：US14290731

申请日：2014-05-29

Applicant: SK hynix Inc.

Inventor： Rae Hyung JEONG ,  Hyun Kyu RYU

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05557 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05673 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/10126 ,  H01L2224/11002 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11845 ,  H01L2224/119 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13673 ,  H01L2224/14051 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L21/304 ,  H01L21/56 ,  H01L2224/034 ,  H01L2224/114 ,  H01L2224/1184 ,  H01L2224/03612

Abstract: A semiconductor device includes a through electrode penetrating a substrate such that a first end portion of the through electrode protrudes from a first surface of the substrate, a passivation layer covering the first surface of the substrate and a sidewall of the first end portion of the through electrode, a bump having a lower portion penetrating the passivation layer and coupled to the first end portion of the through electrode, and a lower metal layer disposed between the bump and the first end portion of the through electrode. The lower metal layer extends onto a sidewall of the bump and has a concave shape.

Abstract translation: 一种半导体器件包括穿透基片的通孔，使得通孔的第一端部从基板的第一表面突出，覆盖基板的第一表面的钝化层和通孔的第一端部的侧壁 电极，具有穿透钝化层的下部并且连接到通孔的第一端部的凸块以及设置在凸块与通孔的第一端部之间的下金属层。 下部金属层延伸到凸块的侧壁上并具有凹形。

公开(公告)号：US20080054457A1

公开(公告)日：2008-03-06

申请号：US11850677

申请日：2007-09-06

Applicant: Mou-Shiung Lin ,  Chiu-Ming Chou

Inventor： Mou-Shiung Lin ,  Chiu-Ming Chou

IPC: H01L23/48

CPC classification number: H01L21/563 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/86 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05166 ,  H01L2224/05553 ,  H01L2224/05568 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/13023 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/13583 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13669 ,  H01L2224/13673 ,  H01L2224/13676 ,  H01L2224/13683 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48673 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48769 ,  H01L2224/48773 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/48873 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06586 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/48869 ,  H01L2224/48744 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A semiconductor chip includes a silicon substrate, a first dielectric layer over said silicon substrate, a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said metallization structure and over said first and second dielectric layers, an opening in said passivation layer exposing a pad of said metallization structure, a polymer bump over said passivation layer, wherein said polymer bump has a thickness of between 5 and 25 micrometers, an adhesion/barrier layer on said pad exposed by said opening, over said passivation layer and on a top surface and a portion of sidewall(s) of said polymer bump, a seed layer on said adhesion/barrier layer; and a third metal layer on said seed layer.

Abstract translation: 半导体芯片包括硅衬底，在所述硅衬底上的第一电介质层，在所述第一介电层上的金属化结构，其中所述金属化结构包括在所述第一金属层上的第一金属层和第二金属层，第二介电层 在所述第一和第二金属层之间的钝化层，在所述金属化结构之上并且在所述第一和第二介电层上方的钝化层，所述钝化层中的开口暴露所述金属化结构的焊盘，所述钝化层上的聚合物凸块，其中所述聚合物凸块 具有5至25微米的厚度，所述焊盘上的粘附/阻挡层，由所述开口暴露在所述钝化层上，所述聚合物凸块的顶表面和侧壁的一部分上，所述 粘合/阻隔层; 以及所述籽晶层上的第三金属层。

公开(公告)号：US08803333B2

公开(公告)日：2014-08-12

申请号：US13544746

申请日：2012-07-09

Applicant: Chen-Hua Yu ,  Da-Yuan Shih ,  Chih-Hang Tung

Inventor： Chen-Hua Yu ,  Da-Yuan Shih ,  Chih-Hang Tung

IPC: H01L29/40 ,  H01L23/48 ,  H01L23/52 ,  H01L23/488

CPC classification number: H01L23/48 ,  H01L23/3185 ,  H01L23/3192 ,  H01L23/488 ,  H01L23/52 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/11466 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/1184 ,  H01L2224/13005 ,  H01L2224/13019 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13618 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13669 ,  H01L2224/13673 ,  H01L2224/13676 ,  H01L2224/29011 ,  H01L2224/29035 ,  H01L2224/2919 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81193 ,  H01L2224/81205 ,  H01L2224/8183 ,  H01L2224/81895 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/206 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A three dimensional (3D) chip stack includes a first chip bonded to a second chip. The first chip includes a first bump structure overlying the first substrate, and the second chip includes a second bump structure overlying the second substrate. The first bump structure is attached to the second bump structure, and a joining region is formed between the first bump structure and the second bump structure. The joining region is a solderless region which includes a noble metal.

Abstract translation: 三维（3D）芯片堆叠包括结合到第二芯片的第一芯片。 第一芯片包括覆盖第一基板的第一凸块结构，并且第二芯片包括覆盖第二基板的第二凸块结构。 第一凸块结构附接到第二凸块结构，并且在第一凸块结构和第二凸块结构之间形成接合区域。 接合区域是包括贵金属的无焊区域。

公开(公告)号：US20130249098A1

公开(公告)日：2013-09-26

申请号：US13894536

申请日：2013-05-15

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West

IPC: H01L23/538

CPC classification number: H01L23/538 ,  H01L21/563 ,  H01L23/481 ,  H01L23/562 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13673 ,  H01L2224/13681 ,  H01L2224/14181 ,  H01L2224/1613 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81002 ,  H01L2224/81005 ,  H01L2224/81007 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01005 ,  H01L2924/01074

Abstract: A method of protecting through substrate via (TSV) die from bonding damage includes providing a substrate including a plurality of TSV die having a topside including active circuitry, a bottomside, and a plurality of TSVs that include an inner metal core that reaches from the topside to protruding TSV tips that extend out from the bottomside. A protective layer is formed on or applied to the bottomside of the TSV die including between and over the protruding TSV tips. The TSV die is bonded with its topside down onto a workpiece having a workpiece surface and its bottomside up and in contact with a bond head. The protective layer reduces damage from the bonding process including warpage of the TSV die by preventing the bond head from making direct contact to the protruding TSV tips.

Abstract translation: 通过衬底通孔（TSV）裸片保护接合损伤的方法包括提供包括多个TSV管芯的衬底，所述TSV管芯具有包括有源电路，底部和多个TSV的顶部，所述TSV包括从顶侧到达的内部金属芯 突出TSV技巧，从底部延伸出来。 在TSV模头的底部上形成保护层，包括在突出的TSV尖端之间和之上。 TSV模具的上下结合到具有工件表面的工件上，并且其底部向上并与接合头接触。 保护层通过防止接合头与突出的TSV尖端直接接触来减少接合过程中的损伤，包括TSV模头的翘曲。

公开(公告)号：US20120306085A1

公开(公告)日：2012-12-06

申请号：US13150899

申请日：2011-06-01

Applicant: Jeffrey Alan West

Inventor： Jeffrey Alan West

IPC: H01L23/538 ,  H01L21/50

CPC classification number: H01L23/538 ,  H01L21/563 ,  H01L23/481 ,  H01L23/562 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13673 ,  H01L2224/13681 ,  H01L2224/14181 ,  H01L2224/1613 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81002 ,  H01L2224/81005 ,  H01L2224/81007 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01005 ,  H01L2924/01074

Abstract: A method of protecting through substrate via (TSV) die from bonding damage includes providing a substrate including a plurality of TSV die having a topside including active circuitry, a bottomside, and a plurality of TSVs that include an inner metal core that reaches from the topside to protruding TSV tips that extend out from the bottomside. A protective layer is formed on or applied to the bottomside of the TSV die including between and over the protruding TSV tips. The TSV die is bonded with its topside down onto a workpiece having a workpiece surface and its bottomside up and in contact with a bond head. The protective layer reduces damage from the bonding process including warpage of the TSV die by preventing the bond head from making direct contact to the protruding TSV tips.

Abstract translation: 通过衬底通孔（TSV）裸片保护接合损伤的方法包括提供包括多个TSV管芯的衬底，所述TSV管芯具有包括有源电路，底部和多个TSV的顶部，所述TSV包括从顶侧到达的内部金属芯 突出TSV技巧，从底部延伸出来。 在TSV模头的底部上形成保护层，包括在突出的TSV尖端之间和之上。 TSV模具的上下结合到具有工件表面的工件上，并且其底部向上并与接合头接触。 保护层通过防止接合头与突出的TSV尖端直接接触来减少接合过程中的损伤，包括TSV模头的翘曲。

公开(公告)号：US20100038777A1

公开(公告)日：2010-02-18

申请号：US12190173

申请日：2008-08-12

Applicant: Mukta G. Farooq ,  Waldemar Walter Kocon ,  Kevin Shawn Petrarca ,  Richard Paul Volant

Inventor： Mukta G. Farooq ,  Waldemar Walter Kocon ,  Kevin Shawn Petrarca ,  Richard Paul Volant

IPC: H01L21/768 ,  H01L23/498

CPC classification number: H01L24/11 ,  H01L21/76852 ,  H01L21/76885 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/13083 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13671 ,  H01L2224/13673 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/01015 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05099

Abstract: A method of forming conductive pillars on a semiconductor wafer in which the conductive pillars are plated with a protecting coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP. Only the side of the conductive pillars are plated. The ends of the conductive pillars are free of the protective plating so that the conductive pillars can be readily joined to the pads of a packaging substrate. Also disclosed is a sidewall-protected conductive pillar having a protective coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP thereon.

Abstract translation: 在半导体晶片上形成导电柱的方法，其中导电柱镀有Ni，Co，Cr，Rh，NiP，NiB，CoWP或CoP的保护涂层。 只有导电柱的一面被电镀。 导电柱的端部没有保护电镀，使得导电柱可以容易地接合到封装基板的焊盘。 还公开了一种侧壁保护的导电柱，其上具有Ni，Co，Cr，Rh，NiP，NiB，CoWP或CoP的保护涂层。

公开(公告)号：US20170345739A1

公开(公告)日：2017-11-30

申请号：US15289187

申请日：2016-10-09

Applicant: International Business Machines Corporation

Inventor： Daniel C. Edelstein ,  Chih-Chao Yang

IPC: H01L23/48 ,  H01L21/822 ,  H01L21/768 ,  H01L27/06 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L21/76856 ,  H01L21/76873 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/53238 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L25/065 ,  H01L27/0688 ,  H01L2224/04 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/05576 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/06102 ,  H01L2224/08146 ,  H01L2224/13009 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/13583 ,  H01L2224/13657 ,  H01L2224/13666 ,  H01L2224/13673 ,  H01L2224/13676 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/13687 ,  H01L2224/29006 ,  H01L2224/29187 ,  H01L2224/32146 ,  H01L2224/73204 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/05442 ,  H01L2224/83 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/0496 ,  H01L2924/01074 ,  H01L2924/0499 ,  H01L2924/01027 ,  H01L2924/0498 ,  H01L2924/01044 ,  H01L2224/08 ,  H01L2224/80 ,  H01L2224/81

Abstract: An advanced through silicon via structure for is described. The device includes a substrate including integrated circuit devices. A high aspect ratio through substrate via is disposed in the substrate. The through substrate via has vertical sidewalls and a horizontal bottom. The substrate has a horizontal field area surrounding the through substrate via. A metallic barrier layer is disposed on the sidewalls of the through substrate via. A surface portion of the metallic barrier layer has been converted to a nitride surface layer by a nitridation process. The nitride surface layer enhances the nucleation of subsequent depositions. A first metal layer fills the through substrate via and has a recess in an upper portion. A second barrier layer is disposed over the recess. A second metal layer is disposed over the second barrier layer and creates a contact.