公开(公告)号：US11973028B2

公开(公告)日：2024-04-30

申请号：US18105945

申请日：2023-02-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun Kim ,  Seokhyun Lee ,  Minjun Bae

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/565 ,  H01L21/76819 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/3128 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0401

Abstract: A method is provided and includes forming a first conductive pattern; forming a photosensitive layer on the first conductive pattern, the photosensitive layer having a first through hole exposing a portion of the first conductive pattern; forming a first via in the first through hole; removing the photosensitive layer; forming a dielectric layer encapsulating the first conductive pattern and the first via, the dielectric layer exposing a top surface of the first via; forming a second conductive pattern on the top surface of the first via, forming a dielectric layer covering the second conductive pattern; etching the dielectric layer to form a second through hole that exposes a portion of the second conductive pattern; forming a second via filling the second through hole and an under bump pad on the second via; and mounting a semiconductor chip on the under bump pad using a connection terminal.

公开(公告)号：US11869835B2

公开(公告)日：2024-01-09

申请号：US17892215

申请日：2022-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Jongyoun Kim ,  Yeonho Jang ,  Jaegwon Jang

IPC: H01L21/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49816

Abstract: A semiconductor package includes a semiconductor chip, a redistribution structure below the semiconductor chip, a first insulating layer below the redistribution structure, a pad below the first insulating layer, the pad being in contact with the redistribution structure, and a bump below the pad, wherein a horizontal maximum length of an upper portion of the pad is greater than a horizontal maximum length of a lower portion of the pad.

公开(公告)号：US20220328414A1

公开(公告)日：2022-10-13

申请号：US17849138

申请日：2022-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package includes a redistribution layer, a semiconductor chip on the redistribution layer, and a molding layer covering a sidewall of the semiconductor chip and a top surface and a sidewall of the redistribution layer. The sidewall of the redistribution layer is inclined with respect to a bottom surface of the redistribution layer, and a sidewall of the molding layer is spaced apart from the sidewall of the redistribution layer.

公开(公告)号：US10685890B2

公开(公告)日：2020-06-16

申请号：US16279118

申请日：2019-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Seokhyun Lee

IPC: H01L21/66 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L23/538

Abstract: A semiconductor package including a redistribution substrate, and a semiconductor chip mounted on the redistribution substrate, the semiconductor chip having a conductive pad on one surface thereof may be provided. The redistribution substrate may include a first passivation pattern on the conductive pad, the first passivation pattern exposing a portion of the conductive pad, and a redistribution pattern covering the portion of the conductive pad exposed by the first passivation pattern and surrounding the first passivation pattern.

公开(公告)号：US11929316B2

公开(公告)日：2024-03-12

申请号：US18111100

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Eungkyu Kim ,  Gwangjae Jeon

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/18

CPC classification number: H01L23/49838 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3107 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/13016 ,  H01L2224/13541 ,  H01L2224/1355 ,  H01L2224/16013 ,  H01L2224/1607 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17055 ,  H01L2224/17517 ,  H01L2224/73204 ,  H01L2224/81345 ,  H01L2224/81815

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a redistribution substrate including dielectric and redistribution patterns, a first substrate pad on the redistribution substrate and penetrating the dielectric pattern to be coupled to the redistribution pattern, a second substrate pad the redistribution substrate and spaced apart from the first substrate pad, a semiconductor chip on the redistribution substrate, a first connection terminal connecting the first substrate pad to one of chip pads of the semiconductor chip, and a second connection terminal connecting the second substrate pad to another one of the chip pads of the semiconductor chip. A top surface of the second substrate pad is located at a higher level than that of a top surface of the first substrate pad. A width of the second substrate pad is less than that of the first substrate pad.

公开(公告)号：US11637081B2

公开(公告)日：2023-04-25

申请号：US17474614

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Jungho Park ,  Seokhyun Lee ,  Yeonho Jang ,  Jaegwon Jang

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/768 ,  H01L25/065

Abstract: A semiconductor package includes a redistribution structure including a redistribution insulating layer and a redistribution pattern, a semiconductor chip provided on a first surface of the redistribution insulation layer and electrically connected to the redistribution pattern, and a lower electrode pad provided on a second surface opposite to the first surface of the redistribution insulating layer, the lower electrode pad including a first portion embedded in the redistribution insulating layer and a second portion protruding from the second surface of the redistribution insulating layer, wherein a thickness of the first portion of the lower electrode pad is greater than a thickness of the second portion of the lower electrode pad.

公开(公告)号：US11600564B2

公开(公告)日：2023-03-07

申请号：US17189964

申请日：2021-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun Kim ,  Seokhyun Lee ,  Minjun Bae

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L21/56 ,  H01L21/768

Abstract: A method is provided and includes forming a first conductive pattern; forming a photosensitive layer on the first conductive pattern, the photosensitive layer having a first through hole exposing a portion of the first conductive pattern; forming a first via in the first through hole; removing the photosensitive layer; forming a dielectric layer encapsulating the first conductive pattern and the first via, the dielectric layer exposing a top surface of the first via; forming a second conductive pattern on the top surface of the first via, forming a dielectric layer covering the second conductive pattern; etching the dielectric layer to form a second through hole that exposes a portion of the second conductive pattern; forming a second via filling the second through hole and an under bump pad on the second via; and mounting a semiconductor chip on the under bump pad using a connection terminal.

公开(公告)号：US11569157B2

公开(公告)日：2023-01-31

申请号：US16946209

申请日：2020-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonho Jang ,  Jongyoun Kim ,  Jungho Park ,  Jaegwon Jang

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor chip; a redistribution insulating layer including a first opening; an external connection bump including a first part in the first opening; a lower bump pad including a first surface in physical contact with the first part of the external connection bump and a second surface opposite to the first surface, wherein the first surface and the redistribution insulating layer partially overlap; and a redistribution pattern that electrically connects the lower bump pad to the semiconductor chip.

公开(公告)号：US11437310B2

公开(公告)日：2022-09-06

申请号：US17085436

申请日：2020-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun Kim

IPC: H05K1/11 ,  H05K1/18 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H05K1/02

Abstract: Provided is a connection structure for a semiconductor package which includes: a first passivation layer having an opening; a first conductive pattern that penetrates the first passivation layer and protrudes upwardly from the first passivation layer; a second passivation layer on the first passivation layer and covering the first conductive pattern; a second conductive pattern on the second passivation layer and electrically connected to the first conductive pattern; a third passivation layer on the second passivation layer and covering the second conductive pattern; and an external terminal in the opening and electrically connected to the first conductive pattern, wherein the first conductive pattern is thicker than the second conductive pattern.

公开(公告)号：US11094636B2

公开(公告)日：2021-08-17

申请号：US16671625

申请日：2019-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegwon Jang ,  Inwon O ,  Jongyoun Kim ,  Seokhyun Lee ,  Yeonho Jang

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/528 ,  H01L23/522 ,  H01L23/66 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package includes a mold substrate, at least one semiconductor chip disposed in the mold substrate and including chip pads, and a redistribution wiring layer covering a first surface of the mold substrate and including a first redistribution wiring and a second redistribution wiring stacked in at least two levels to be electrically connected to the chip pads. The first redistribution wiring includes a signal line extending in a first region, and the second redistribution wiring includes a ground line in a second region overlapping with the first region. The ground line has a plurality of through holes of polygonal column shapes.