公开(公告)号：US10950539B2

公开(公告)日：2021-03-16

申请号：US16351709

申请日：2019-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun Kim ,  Seokhyun Lee ,  Minjun Bae

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L21/56 ,  H01L21/768

Abstract: A redistribution subtrate, a method of fabricating the same, and a semiconductor package are provided. The method including forming a first conductive pattern; forming a first photosensitive layer on the first conductive pattern, the first photosensitive layer having a first through hole exposing a first portion of the first conductive pattern; forming a first via in the first through hole; removing the first photosensitive layer; forming a first dielectric layer that encapsulates the first conductive pattern and the first via, the first dielectric layer exposing a top surface of the first via; and forming a second conductive pattern on the top surface of the first via.

公开(公告)号：US12014975B2

公开(公告)日：2024-06-18

申请号：US17453243

申请日：2021-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaegwon Jang ,  Kyoung Lim Suk ,  Minjun Bae

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/04 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/16227

Abstract: A semiconductor package includes a redistribution substrate and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an insulating layer, and first, second, and third redistribution patterns disposed in the insulating layer. The first to third redistribution patterns are sequentially stacked in an upward direction and are electrically connected to each other. Each of the first to third redistribution patterns includes a wire portion that extends parallel to the top surface of the redistribution substrate. Each of the first and third redistribution patterns further includes a via portion that extends from the wire portion in a direction perpendicular to the top surface of the redistribution substrate. The second redistribution pattern furthers include first fine wire patterns that are less wide than the wire portion of the second redistribution pattern.

公开(公告)号：US11973028B2

公开(公告)日：2024-04-30

申请号：US18105945

申请日：2023-02-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun Kim ,  Seokhyun Lee ,  Minjun Bae

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/565 ,  H01L21/76819 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/3128 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0401

Abstract: A method is provided and includes forming a first conductive pattern; forming a photosensitive layer on the first conductive pattern, the photosensitive layer having a first through hole exposing a portion of the first conductive pattern; forming a first via in the first through hole; removing the photosensitive layer; forming a dielectric layer encapsulating the first conductive pattern and the first via, the dielectric layer exposing a top surface of the first via; forming a second conductive pattern on the top surface of the first via, forming a dielectric layer covering the second conductive pattern; etching the dielectric layer to form a second through hole that exposes a portion of the second conductive pattern; forming a second via filling the second through hole and an under bump pad on the second via; and mounting a semiconductor chip on the under bump pad using a connection terminal.

公开(公告)号：US11894338B2

公开(公告)日：2024-02-06

申请号：US17592947

申请日：2022-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Park ,  Jungho Park ,  Dahye Kim ,  Minjun Bae

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L24/94 ,  H01L23/3121 ,  H01L24/14 ,  H01L25/0657

Abstract: Provided are a wafer level package and a method of manufacturing the same, wherein an underfill sufficiently fills a space between a redistribution substrate and a semiconductor chip, thereby reducing warpage. The wafer level package includes a redistribution substrate including at least one redistribution layer (RDL), a semiconductor chip on the redistribution substrate, and an underfill filling a space between the redistribution substrate and the semiconductor chip. The underfill covers side surfaces of the semiconductor chip. The redistribution substrate includes a trench having a line shape and extending in a first direction along a first side surface of the semiconductor chip.

公开(公告)号：US11948872B2

公开(公告)日：2024-04-02

申请号：US17509224

申请日：2021-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Minjun Bae ,  Hyeonseok Lee ,  Gwangjae Jeon

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/18 ,  H01L23/34

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/18 ,  H01L23/34 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/73204

Abstract: Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.

公开(公告)号：US20210020505A1

公开(公告)日：2021-01-21

申请号：US16797990

申请日：2020-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegwon Jang ,  Seokhyun Lee ,  Jongyoun Kim ,  Minjun Bae

IPC: H01L21/768 ,  H01L23/00 ,  H01L21/56

Abstract: A method of manufacturing a semiconductor package is provided including forming a lower redistribution layer. A conductive post is formed on the lower redistribution layer. A semiconductor chip is mounted on the lower redistribution layer. A molding member is formed on the lower redistribution layer. An upper surface of the molding member is at a level lower than an upper surface of the conductive post. An insulating layer is formed on the molding member. An upper surface of the insulating layer is at a level higher than the upper surface of the conductive post. The insulating layer is etched to expose the upper surface of the conductive post. An upper redistribution layer is formed on the insulating layer. The upper redistribution layer is electrically connected to the conductive post.

公开(公告)号：US12230556B2

公开(公告)日：2025-02-18

申请号：US18588699

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Minjun Bae ,  Hyeonseok Lee ,  Gwangjae Jeon

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/18 ,  H01L23/34

Abstract: Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.

公开(公告)号：US20240128155A1

公开(公告)日：2024-04-18

申请号：US18379841

申请日：2023-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjun Bae ,  Eungkyu Kim ,  Jongyoun Kim

IPC: H01L23/373 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/3738 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0655 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83896 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441

Abstract: Provided is a semiconductor package comprising a redistribution structure including a redistribution pattern and a redistribution insulation layer covering the redistribution pattern, a semiconductor chip disposed on the redistribution structure and having an active surface and an inactive surface opposite to the active surface, a molding layer disposed on the redistribution structure and covering at least a portion of the semiconductor chip, and a silicon heat dissipation structure disposed on the semiconductor chip, wherein the silicon heat dissipation structure is bonded to the semiconductor chip through silicon (Si)-to-Si direct bonding.

公开(公告)号：US20210183766A1

公开(公告)日：2021-06-17

申请号：US17189964

申请日：2021-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun Kim ,  Seokhyun Lee ,  Minjun Bae

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L21/56 ,  H01L21/768

Abstract: A method is proivded and includes forming a first conductive pattern; forming a photosensitive layer on the first conductive pattern, the photosensitive layer having a first through hole exposing a portion of the first conductive pattern; forming a first via in the first through hole; removing the photosensitive layer; forming a dielectric layer encapsulating the first conductive pattern and the first via, the dielectric layer exposing a top surface of the first via; forming a second conductive pattern on the top surface of the first via, forming a dielectric layer covering the second conductive pattern; etching the dielectric layer to form a second through hole that exposes a portion of the second conductive pattern; forming a second via filling the second through hole and an under bump pad on the second via; and mounting a semiconductor chip on the under bump pad using a connection terminal.

公开(公告)号：US20230187345A1

公开(公告)日：2023-06-15

申请号：US18105945

申请日：2023-02-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun KIM ,  Seokhyun Lee ,  Minjun Bae

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L24/09 ,  H01L24/17 ,  H01L23/3128 ,  H01L23/5283 ,  H01L21/565 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76819 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/0231 ,  H01L2224/02373

Abstract: A method is provided and includes forming a first conductive pattern; forming a photosensitive layer on the first conductive pattern, the photosensitive layer having a first through hole exposing a portion of the first conductive pattern; forming a first via in the first through hole; removing the photosensitive layer; forming a dielectric layer encapsulating the first conductive pattern and the first via, the dielectric layer exposing a top surface of the first via; forming a second conductive pattern on the top surface of the first via, forming a dielectric layer covering the second conductive pattern; etching the dielectric layer to form a second through hole that exposes a portion of the second conductive pattern; forming a second via filling the second through hole and an under bump pad on the second via; and mounting a semiconductor chip on the under bump pad using a connection terminal.