公开(公告)号：US20090244874A1

公开(公告)日：2009-10-01

申请号：US12059133

申请日：2008-03-31

Applicant: Ravi Mahajan ,  Sandeep Sane

Inventor： Ravi Mahajan ,  Sandeep Sane

IPC: H05K7/02 ,  H01L21/50

CPC classification number: H05K1/142 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15192 ,  H05K1/141 ,  H05K1/181 ,  H05K1/183 ,  H05K2201/0187 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05647

Abstract: A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.

Abstract translation: 微电子封装包括衬底（110），嵌入衬底中的硅贴片（120），在硅贴片的第一位置处的第一互连结构（131）和在第二位置处的第二互连结构（132） 硅贴片以及将第一互连结构和第二互连结构彼此连接的硅贴片中的导电线（150）。

公开(公告)号：US08441809B2

公开(公告)日：2013-05-14

申请号：US13161538

申请日：2011-06-16

Applicant: Ravi Mahajan ,  Sandeep Sane

Inventor： Ravi Mahajan ,  Sandeep Sane

IPC: H05K7/02 ,  H01L21/78 ,  H01L21/50

CPC classification number: H05K1/142 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15192 ,  H05K1/141 ,  H05K1/181 ,  H05K1/183 ,  H05K2201/0187 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05647

Abstract: A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.

Abstract translation: 微电子封装包括衬底（110），嵌入衬底中的硅贴片（120），在硅贴片的第一位置处的第一互连结构（131）和在第二位置处的第二互连结构（132） 硅贴片以及将第一互连结构和第二互连结构彼此连接的硅贴片中的导电线（150）。

公开(公告)号：US08064224B2

公开(公告)日：2011-11-22

申请号：US12059133

申请日：2008-03-31

Applicant: Ravi Mahajan ,  Sandeep Sane

Inventor： Ravi Mahajan ,  Sandeep Sane

IPC: H05K7/02 ,  H01L21/78 ,  H01L21/50

CPC classification number: H05K1/142 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15192 ,  H05K1/141 ,  H05K1/181 ,  H05K1/183 ,  H05K2201/0187 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05647

Abstract: A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.

Abstract translation: 微电子封装包括衬底（110），嵌入衬底中的硅贴片（120），在硅贴片的第一位置处的第一互连结构（131）和在第二位置处的第二互连结构（132） 硅贴片以及将第一互连结构和第二互连结构彼此连接的硅贴片中的导电线（150）。

公开(公告)号：US20110241208A1

公开(公告)日：2011-10-06

申请号：US13161538

申请日：2011-06-16

Applicant: Ravi Mahajan ,  Sandeep Sane

Inventor： Ravi Mahajan ,  Sandeep Sane

IPC: H01L23/48

CPC classification number: H05K1/142 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15192 ,  H05K1/141 ,  H05K1/181 ,  H05K1/183 ,  H05K2201/0187 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05647

Abstract: A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.

Abstract translation: 微电子封装包括衬底（110），嵌入衬底中的硅贴片（120），在硅贴片的第一位置处的第一互连结构（131）和在第二位置处的第二互连结构（132） 硅贴片以及将第一互连结构和第二互连结构彼此连接的硅贴片中的导电线（150）。

公开(公告)号：US06903929B2

公开(公告)日：2005-06-07

申请号：US10404213

申请日：2003-03-31

Applicant: Ravi Prasher ,  Ravi Mahajan

Inventor： Ravi Prasher ,  Ravi Mahajan

IPC: H01L23/40 ,  H01L23/473 ,  H05K7/20

CPC classification number: H01L23/427 ,  H01L23/4006 ,  H01L23/473 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Integrated circuit (IC) packages employing two-phase microchannel heat exchangers for cooling the packages' IC dies and cooling systems employing the same are disclosed. The heat exchangers include thermal masses having a plurality of microchannels formed therein. In one set of configurations, the IC die is thermally coupled to a pair of microchannel heat exchangers disposed on opposite sides of the die. Top-side microchannel heat exchangers include a thermal mass having a plurality of open microchannels having wall bases that are hermetically sealed with the top surface of the die, thus forming a plurality of closed microchannels. Alternatively, a separate microchannel heat exchanger is thermally coupled to an IC die and operatively coupled to the IC die via coupling to a substrate on which the IC die is mounted. Bottom-side heat exchangers include substrates and chip carriers having microchannels formed therethrough that are thermally coupled to the IC die. The cooling systems employ a plurality of microchannel heat exchangers to cool selected electronic components.

Abstract translation: 公开了采用两相微通道热交换器来冷却封装IC芯片的集成电路（IC）封装以及采用其的冷却系统。 热交换器包括其中形成有多个微通道的热质量。 在一组配置中，IC管芯热耦合到设置在管芯的相对侧上的一对微通道热交换器。 顶侧微通道热交换器包括具有多个开口微通道的热质，其具有与模具顶表面气密密封的壁基，从而形成多个闭合微通道。 或者，单独的微通道热交换器热耦合到IC管芯，并且通过耦合到IC芯片上安装有IC管芯的基板而可操作地耦合到IC管芯。 底侧热交换器包括具有热连接到IC管芯的通过其形成的微通道的衬底和芯片载体。 冷却系统采用多个微通道热交换器来冷却选定的电子部件。

公开(公告)号：US20070164427A1

公开(公告)日：2007-07-19

申请号：US11322495

申请日：2005-12-30

Applicant: Ioan Sauciuc ,  Ravi Mahajan

Inventor： Ioan Sauciuc ,  Ravi Mahajan

IPC: H01L23/34

CPC classification number: H01L23/427 ,  F28D15/00 ,  F28D15/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention discloses a method of confining a liquid metal alloy within a closed-loop system; distributing a first portion of the liquid metal alloy in a cavity within the closed-loop system; turning on an electromagnet to generate a magnetic field to permeate flexible sidewalls of the cavity; attracting the liquid metal alloy in the cavity towards the electromagnet to expand the flexible sidewalls; inducing a second portion of the liquid metal alloy to enter the cavity from an inlet end of a heat pipe within the closed-loop system; turning off the electromagnet; repelling the liquid metal alloy in the cavity away from the electromagnet to contract the flexible sidewalls; and inducing a third portion of the liquid metal alloy to exit the cavity to an outlet end of the heat pipe.

Abstract translation: 本发明公开了一种将液态金属合金限制在闭环系统内的方法; 将所述液态金属合金的第一部分分布在所述闭环系统内的空腔中; 打开电磁体以产生磁场以渗透空腔的柔性侧壁; 将空腔中的液态金属合金吸引到电磁体以膨胀柔性侧壁; 引起所述液态金属合金的第二部分从所述闭环系统内的热管的入口端进入所述空腔; 关闭电磁铁; 将空腔中的液态金属合金排斥离开电磁体以收缩柔性侧壁; 并且引起液态金属合金的第三部分将空腔排出到热管的出口端。

公开(公告)号：US20050093138A1

公开(公告)日：2005-05-05

申请号：US10698749

申请日：2003-10-31

Applicant: Sarah Kim ,  R. List ,  James Maveety ,  Alan Myers ,  Quat Vu ,  Ravi Prasher ,  Ravi Mahajan ,  Gilroy Vandentop

Inventor： Sarah Kim ,  R. List ,  James Maveety ,  Alan Myers ,  Quat Vu ,  Ravi Prasher ,  Ravi Mahajan ,  Gilroy Vandentop

IPC: H01L23/473 ,  H01L23/34

CPC classification number: H01L23/473 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2224/82

Abstract: An integrated circuit to be cooled may be abutted in face-to-face abutment with a cooling integrated circuit. The cooling integrated circuit may include electroosmotic pumps to pump cooling fluid through the cooling integrated circuits via microchannels to thereby cool the heat generating integrated circuit. The electroosmotic pumps may be fluidically coupled to external radiators which extend upwardly away from a package including the integrated circuits. In particular, the external radiators may be mounted on tubes which extend the radiators away from the package.

Abstract translation: 要冷却的集成电路可以与冷却集成电路面对面邻接。 冷却集成电路可以包括电渗泵，以通过微通道将冷却流体泵送通过冷却集成电路，从而冷却发热集成电路。 电渗泵可以流体耦合到从包括集成电路的包装向上延伸的外部散热器。 特别地，外部散热器可以安装在使散热器远离封装的管上。

公开(公告)号：US20050029637A1

公开(公告)日：2005-02-10

申请号：US10638038

申请日：2003-08-08

Applicant: Chuan Hu ,  Gregory Chrysler ,  Ravi Mahajan

Inventor： Chuan Hu ,  Gregory Chrysler ,  Ravi Mahajan

IPC: H01L23/38 ,  H01L23/495

CPC classification number: H01L23/38 ,  H01L2224/73253 ,  H01L2924/16195

Abstract: A microelectronic die is provided having an integrated thermoelectric module. The microelectronic die has a die substrate, a microelectronic circuit formed on a front side of the die substrate, and the thermoelectric module on a backside of the die substrate. Vias in the substrate interconnect the thermoelectric module with power and ground planes on the front side of the die substrate.

Abstract translation: 提供具有集成热电模块的微电子管芯。 微电子管芯具有管芯基板，形成在管芯基板的前侧的微电子电路，以及位于管芯基板背面的热电模块。 衬底中的通孔将热电模块与模具衬底的前侧上的电源和接地平面互连。

公开(公告)号：US06700209B1

公开(公告)日：2004-03-02

申请号：US09474746

申请日：1999-12-29

Applicant: George F. Raiser ,  Bob Sundahl ,  Ravi Mahajan

Inventor： George F. Raiser ,  Bob Sundahl ,  Ravi Mahajan

IPC: H01L2329

CPC classification number: H01L24/31 ,  H01L21/563 ,  H01L23/3121 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/83951 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2224/05599

Abstract: An integrated circuit package that contains an underfill material between an integrated circuit and a substrate. The integrated circuit may be mounted to the substrate with solder bumps in a C4 process. The underfill material may extend from an edge of the integrated circuit a length that is no less than approximately 25% of the length between the integrated circuit edge and the integrated circuit center. It has been discovered that a length greater than approximately 25% does not provide a significant reduction in the strain of the solder bumps.

Abstract translation: 集成电路封装，其在集成电路和衬底之间包含底部填充材料。 集成电路可以通过C4工艺中的焊料凸块安装到基板上。 底部填充材料可以从集成电路的边缘延伸的长度不小于集成电路边缘和集成电路中心之间的长度的大约25％。 已经发现，大于约25％的长度不能显着降低焊料凸块的应变。

公开(公告)号：US06173489B1

公开(公告)日：2001-01-16

申请号：US09032628

申请日：1998-02-27

Applicant: John F. McMahon ,  Ravi Mahajan

Inventor： John F. McMahon ,  Ravi Mahajan

IPC: H05K334

CPC classification number: H01L23/49822 ,  H01L23/49816 ,  H01L2224/16 ,  H05K1/0271 ,  H05K1/118 ,  H05K3/0058 ,  H05K3/3436 ,  H05K2201/068 ,  H05K2201/09109 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: A flip chip integrated circuit package which provides stress relief for the solder bumps of the package. The package includes an integrated circuit that is mounted to a substrate. The integrated circuit is attached to a plurality of bond pads of the substrate by a number of corresponding solder bumps. The substrate has a first layer that is attached to a second layer. An area that is located between the layers and adjacent to the bond pads is left unattached so that a portion of the first layer can move independent of the remaining portion of the substrate. The unattached area allows the integrated circuit to “float” and expand at a different rate than the substrate when the package is thermally cycled.

Abstract translation: 一种倒装芯片集成电路封装，为封装的焊料凸块提供应力消除。 封装包括一个安装在基板上的集成电路。 集成电路通过多个对应的焊料凸点附着到衬底的多个接合焊盘。 衬底具有附接到第二层的第一层。 位于层之间并且与接合焊盘相邻的区域不附着，使得第一层的一部分可以独立于衬底的剩余部分移动。 未连接区域允许集成电路在封装热循环时以与衬底不同的速率“漂浮”并膨胀。