Invention Grant
- Patent Title: Microelectronic package containing silicon connecting region for high density interconnects, and method of manufacturing same
- Patent Title (中): 含有用于高密度互连的硅连接区域的微电子封装及其制造方法
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Application No.: US13161538Application Date: 2011-06-16
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Publication No.: US08441809B2Publication Date: 2013-05-14
- Inventor: Ravi Mahajan , Sandeep Sane
- Applicant: Ravi Mahajan , Sandeep Sane
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Kenneth A. Nelson
- Main IPC: H05K7/02
- IPC: H05K7/02 ; H01L21/78 ; H01L21/50
Abstract:
A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.
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