Invention Application
- Patent Title: Flip Chip Interconnection having Narrow Interconnection Sites on the Substrate
- Patent Title (中): 倒装芯片互连在基板上具有窄的互连位置
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Application No.: US13645397Application Date: 2012-10-04
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Publication No.: US20130026628A1Publication Date: 2013-01-31
- Inventor: Rajendra D. Pendse
- Applicant: STATS CHIPPAC, LTD.
- Applicant Address: SG Singapore
- Assignee: STATS CHIPPAC, LTD.
- Current Assignee: STATS CHIPPAC, LTD.
- Current Assignee Address: SG Singapore
- Main IPC: H01L21/60
- IPC: H01L21/60 ; H01L23/498

Abstract:
A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the die to be attached. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having narrow interconnect pads on electrically conductive traces in a die attach surface, in which the bumps are mated onto the narrow pads on the traces.
Public/Granted literature
- US09159665B2 Flip chip interconnection having narrow interconnection sites on the substrate Public/Granted day:2015-10-13
Information query
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