公开(公告)号：US12114491B2

公开(公告)日：2024-10-08

申请号：US18377418

申请日：2023-10-06

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Hsih-Yang Chiu

IPC分类号： H10B20/20

CPC分类号： H10B20/20

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first dielectric layer on a substrate; first/second upper short axis portions extending along a first direction, separated from each other, and on the first dielectric layer; a common source region in the substrate and adjacent to the first/second upper short axis portions; a first branch drain region in the substrate, adjacent to the first upper short axis portion, and opposite to the common source region; a second branch drain region in the substrate, adjacent to the second upper short axis portion, and opposite to the common source region; and a top electrode on the first dielectric layer and topographically above the first branch drain region and the second branch drain region. The top electrode, the first dielectric layer, and the first/second branch drain regions together configure a programmable unit.

公开(公告)号：US11955427B2

公开(公告)日：2024-04-09

申请号：US17643406

申请日：2021-12-08

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Hsih-Yang Chiu

IPC分类号： H01L23/525 ,  H01L21/02 ,  H01L27/08

CPC分类号： H01L23/5252 ,  H01L21/0223 ,  H01L21/02255 ,  H01L27/0802

摘要： An electrical fuse matrix includes a plurality of anti-fuse structures, a plurality of top metal plates, and a plurality of bottom metal plates. The anti-fuse structures are arranged in a matrix, and each of the anti-fuse structure includes a top conductive structure, a bottom conductive structure, and a dielectric film disposed between the top conductive structure and the bottom conductive structure. The anti-fuse structure has an hourglass shape. The top metal plates are disposed on the top conductive structures. The bottom metal plates are disposed on the bottom conductive structures.

公开(公告)号：US11894247B2

公开(公告)日：2024-02-06

申请号：US17520556

申请日：2021-11-05

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Hsih-Yang Chiu

IPC分类号： H01L21/67 ,  H01L23/528 ,  H01L23/00

CPC分类号： H01L21/67121 ,  H01L21/67063 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/80 ,  H01L2224/02163 ,  H01L2224/0361 ,  H01L2224/08145 ,  H01L2224/80004

摘要： The present disclosure provides a mothed of method of manufacturing a semiconductor device. The method includes steps of forming a dielectric layer on a substrate; etching the dielectric layer to create a plurality of openings in the dielectric layer; applying a sacrificial layer in at least one of the openings to cover at least a portion of the dielectric layer; forming at least one first conductive feature in the openings where the sacrificial layer is disposed and a plurality of bases in the openings where the sacrificial layer is not disposed; removing the sacrificial layer to form at least one air gap in the dielectric layer; and forming a plurality of protrusions on the bases.

公开(公告)号：US11664364B2

公开(公告)日：2023-05-30

申请号：US17212620

申请日：2021-03-25

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Hsih-Yang Chiu

IPC分类号： H01L25/00 ,  H01L23/00 ,  H01L21/768 ,  H01L25/18 ,  H01L25/065

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L2224/0384 ,  H01L2224/03831 ,  H01L2224/05551 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/0603 ,  H01L2224/06517 ,  H01L2224/0801 ,  H01L2224/08146 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/32145 ,  H01L2224/8013 ,  H01L2224/8092 ,  H01L2224/80895 ,  H01L2224/80951 ,  H01L2224/8313 ,  H01L2224/83896 ,  H01L2224/9202 ,  H01L2224/9211 ,  H01L2225/06544

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, a second semiconductor structure, a through semiconductor via, and an insulation layer. The first semiconductor structure includes a first circuit layer and a first main bonding layer in the first circuit layer and substantially coplanar with a front face of the first circuit layer. The second semiconductor structure includes a second circuit layer on the first circuit layer and a second main bonding layer in the second circuit layer, and topologically aligned with and contacted to the first main bonding layer. The through semiconductor via is along the second semiconductor structure and the first and second main bonding layer, and extending to the first circuit layer. The insulation layer is positioned on a sidewall of the through semiconductor via.

公开(公告)号：US11482490B1

公开(公告)日：2022-10-25

申请号：US17228172

申请日：2021-04-12

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Hsih-Yang Chiu

IPC分类号： H01L23/525

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first electrode including a first vertical column, and a first bottom branch unit at a first vertical level and including a first set of bottom plates extending from the first vertical column and parallel to a first direction; two second electrodes respectively including a second vertical column, and a second bottom branch unit at a second vertical level higher than the first vertical level and including a first set of bottom plates extending from the second vertical column and parallel to the first direction; and a first insulation layer positioned between the first and second bottom branch unit. The first sets of bottom plates of the first and second bottom branch unit are partially overlapped. The first insulation layer and the first and second electrode together configure a programmable structure.

公开(公告)号：US11469175B2

公开(公告)日：2022-10-11

申请号：US17149032

申请日：2021-01-14

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Hsih-Yang Chiu ,  Tse-Yao Huang

IPC分类号： H01L23/00 ,  H01L23/525 ,  H01L21/3215 ,  H01L23/535 ,  H01L21/28 ,  H01L29/92 ,  H01L29/40 ,  H01L23/532 ,  H01L29/49

摘要： The present application discloses a semiconductor device with a programmable unit and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a bottom conductive layer positioned in the substrate, an insulation layer positioned on the substrate, a first conductive layer positioned on the insulation layer and above the bottom conductive layer, a second conductive layer positioned on the insulation layer and above the bottom conductive layer and spaced apart from the first conductive layer, a conductive plug electrically coupled to the bottom conductive layer, and a top conductive layer electrically coupled to the first conductive layer and the second conductive layer. The first conductive layer has a first work function and the second conductive layer has a second work function different from the first work function. The bottom conductive layer, the insulation layer, the first conductive layer, and the second conductive layer together configure a programmable unit.

公开(公告)号：US11309282B2

公开(公告)日：2022-04-19

申请号：US17012295

申请日：2020-09-04

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Hsih-Yang Chiu

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00

摘要： The present disclosure provides a method for manufacturing a semiconductor package. The method includes steps of providing semiconductor wafer having a plurality of device chips disposed thereon, wherein each of the plurality of device chips has an active area and an inactive area arranged around the active area; forming a plurality of the openings, wherein each of the plurality of openings is formed in a back surface of the semiconductor wafer and forms an opening into the inactive area; and disposing a protecting material within the openings and over the back surface of the semiconductor wafer.

公开(公告)号：US10886236B1

公开(公告)日：2021-01-05

申请号：US16544887

申请日：2019-08-19

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ting-Cih Kang ,  Hsih-Yang Chiu

IPC分类号： H01L23/528 ,  H01L23/552 ,  H01L23/522

摘要： An interconnect structure includes a first and second insulating layer, a first and second conductive line, and a first, second, and third conductive via. The second insulating layer is disposed on the first insulating layer. The first conductive line including a first and second portion, and the first, second, and the third conductive vias are embedded in the first insulating layer. The second conductive line including a third portion and fourth portion is embedded in the second insulating layer. The first conductive via connects the first and third portions. The second conductive via connects the second and third portions. The third conductive via connects the second and fourth portions. A first cross-sectional area surrounded by the first, second, third portions, the first, second conductive vias is substantially equal to a second cross-sectional area surrounded by the second, third, fourth portions, the second, third conductive vias.

公开(公告)号：US10804184B2

公开(公告)日：2020-10-13

申请号：US16281360

申请日：2019-02-21

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Hsih-Yang Chiu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/40 ,  H01L21/768

摘要： The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate, a restraint layer, a plurality of contact plugs, and a plurality of through silicon vias. The restraint layer is disposed on the semiconductor substrate, and the contact plugs are inserted into the restraint layer. The through silicon vias extend from a bottom surface of the semiconductor substrate to a front surface opposite to the back surface and the through silicon vias are in contact with the contact plugs, respectively.

公开(公告)号：US10522466B1

公开(公告)日：2019-12-31

申请号：US16153073

申请日：2018-10-05

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Hsih-Yang Chiu

IPC分类号： H01L23/528 ,  H01L23/48 ,  H01L23/482 ,  H01L21/768 ,  H01L21/683 ,  H01L21/304 ,  H01L21/283

摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a target layer, a plurality of metal pads, a plurality of conductive lines, a plurality of conductive plugs, an isolating liner, and a plurality of metal contacts. The semiconductor substrate has a front surface, a rear surface opposite to the front surface, and an implanted region connected to the rear surface. The target layer is disposed over the front surface. The metal pads are disposed over the target layer. The plurality of conductive lines are disposed within the semiconductor substrate and the target layer and connected to the metal pads. The conductive plugs are disposed in the implanted region. The isolating liner encircles the conductive plugs. The metal contacts are disposed over the conductive lines and the conductive plugs.