公开(公告)号：US20170086304A1

公开(公告)日：2017-03-23

申请号：US14859026

申请日：2015-09-18

申请人： Delaware Capital Formation, Inc.

发明人： Mark Hahn

IPC分类号： H05K3/10 ,  B23K26/0622 ,  B23K9/09 ,  B23K26/21 ,  H05K1/18 ,  B23K9/167

CPC分类号： H05K3/103 ,  B23K9/0043 ,  B23K9/091 ,  B23K9/092 ,  B23K9/167 ,  B23K9/23 ,  B23K26/0622 ,  B23K26/21 ,  B23K26/22 ,  B23K26/32 ,  B23K2101/38 ,  B23K2103/00 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/05 ,  H01L24/07 ,  H01L24/08 ,  H01L24/09 ,  H01L24/42 ,  H01L24/44 ,  H01L24/45 ,  H01L24/46 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02163 ,  H01L2224/02185 ,  H01L2224/04042 ,  H01L2224/45147 ,  H01L2224/45639 ,  H01L2224/48476 ,  H01L2224/80007 ,  H01L2224/80009 ,  H01L2224/8019 ,  H01L2224/8034 ,  H01L2924/00014 ,  H05K1/18 ,  H05K3/328 ,  H05K2201/10242 ,  H05K2201/10265 ,  H05K2201/10287 ,  H01L2224/05599 ,  H01L2224/85399

摘要： A method of forming a microelectronic device structure comprises coiling a portion of a wire up and around at least one sidewall of a structure protruding from a substrate. At least one interface between an upper region of the structure and an upper region of the coiled portion of the wire is welded to form a fused region between the structure and the wire.

公开(公告)号：US20090079070A1

公开(公告)日：2009-03-26

申请号：US11858749

申请日：2007-09-20

申请人： Yaojian Lin ,  Xu Sheng Bao

发明人： Yaojian Lin ,  Xu Sheng Bao

IPC分类号： H01L23/52 ,  H01L21/60

CPC分类号： H05K3/3452 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02123 ,  H01L2224/02163 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13011 ,  H01L2224/13016 ,  H01L2224/131 ,  H01L2224/1613 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K1/112 ,  H05K3/3436 ,  H05K3/3457 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/099 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/014

摘要： A flip chip style semiconductor package has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate. An under bump metallization (UBM) layer is in electrical contact with the contact pad. A passivation layer is formed over the substrate. In one case, the UBM layer is disposed above the passivation layer. Alternatively, the passivation layer is disposed above the UBM layer. A portion of the passivation layer is removed to create a passivation island. The passivation island is centered with respect to the contact pad with its top surface devoid of the UBM layer. A solder bump is formed over the passivation island in electrical contact with the UBM layer. The passivation island forms a void in the solder bump for stress relief. The UBM layer may include a redistribution layer such that the passivation island is offset from the contact pad.

摘要翻译： 倒装片式半导体封装具有在其上形成有多个有源器件的衬底。 在基板上形成接触垫。 凸块下金属化（UBM）层与接触焊盘电接触。 钝化层形成在衬底上。 在一种情况下，UBM层设置在钝化层上方。 或者，钝化层设置在UBM层上。 去除钝化层的一部分以产生钝化岛。 钝化岛相对于接触焊盘居中，其顶表面没有UBM层。 在与UBM层电接触的钝化岛上形成焊料凸点。 钝化岛在焊料凸块中形成空隙以消除应力。 UBM层可以包括再分布层，使得钝化岛从接触垫偏移。

公开(公告)号：US20170275153A1

公开(公告)日：2017-09-28

申请号：US15080356

申请日：2016-03-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Ming Chen ,  Ping-Yin Liu ,  Chung-Yi Yu ,  Yeur-Luen Tu

IPC分类号： B81B7/00 ,  B81C1/00 ,  H01L23/00

CPC分类号： B81B7/007 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/052 ,  B81C1/00269 ,  B81C1/00357 ,  B81C2201/013 ,  B81C2203/0109 ,  B81C2203/019 ,  B81C2203/036 ,  H01L24/03 ,  H01L24/09 ,  H01L2224/02163 ,  H01L2224/05082 ,  H01L2224/05109 ,  H01L2224/05117 ,  H01L2224/05124 ,  H01L2224/05138 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2924/01014 ,  H01L2924/01032 ,  H01L2924/1461

摘要： An embodiment method includes forming a first plurality of bond pads on a device substrate, depositing a spacer layer over and extending along sidewalls of the first plurality of bond pads, and etching the spacer layer to remove lateral portions of the spacer layer and form spacers on sidewalls of the first plurality of bond pads. The method further includes bonding a cap substrate including a second plurality of bond pads to the device substrate by bonding the first plurality of bond pads to the second plurality of bond pads.

公开(公告)号：US09717148B2

公开(公告)日：2017-07-25

申请号：US14859026

申请日：2015-09-18

申请人： Delaware Capital Formation, Inc.

发明人： Mark Hahn

IPC分类号： H05K3/10 ,  H05K1/18 ,  B23K9/167 ,  B23K9/09 ,  H01L23/00 ,  B23K26/21 ,  B23K26/0622

CPC分类号： H05K3/103 ,  B23K9/0043 ,  B23K9/091 ,  B23K9/092 ,  B23K9/167 ,  B23K9/23 ,  B23K26/0622 ,  B23K26/21 ,  B23K26/22 ,  B23K26/32 ,  B23K2101/38 ,  B23K2103/00 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/05 ,  H01L24/07 ,  H01L24/08 ,  H01L24/09 ,  H01L24/42 ,  H01L24/44 ,  H01L24/45 ,  H01L24/46 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02163 ,  H01L2224/02185 ,  H01L2224/04042 ,  H01L2224/45147 ,  H01L2224/45639 ,  H01L2224/48476 ,  H01L2224/80007 ,  H01L2224/80009 ,  H01L2224/8019 ,  H01L2224/8034 ,  H01L2924/00014 ,  H05K1/18 ,  H05K3/328 ,  H05K2201/10242 ,  H05K2201/10265 ,  H05K2201/10287 ,  H01L2224/05599 ,  H01L2224/85399

摘要： A method of forming a microelectronic device structure comprises coiling a portion of a wire up and around at least one sidewall of a structure protruding from a substrate. At least one interface between an upper region of the structure and an upper region of the coiled portion of the wire is welded to form a fused region between the structure and the wire.

公开(公告)号：US20170207139A1

公开(公告)日：2017-07-20

申请号：US15478133

申请日：2017-04-03

申请人： Micron Technology, Inc.

发明人： Owen R. Fay ,  Kyle K. Kirby ,  Luke G. England ,  Jaspreet S. Gandhi

IPC分类号： H01L21/66 ,  H01L23/00

CPC分类号： H01L22/32 ,  H01L22/14 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02163 ,  H01L2224/0391 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/05552

摘要： An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad.

公开(公告)号：US09111951B2

公开(公告)日：2015-08-18

申请号：US14172229

申请日：2014-02-04

申请人： SEIKO INSTRUMENTS INC.

发明人： Keisuke Uemura ,  Jun Osanai

IPC分类号： H01L23/04 ,  H01L23/00 ,  H01L23/48 ,  H01L23/29

CPC分类号： H01L23/564 ,  H01L23/293 ,  H01L23/481 ,  H01L24/05 ,  H01L2224/02163 ,  H01L2224/02233 ,  H01L2224/02255 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/00014

摘要： Provided is a semiconductor device configured to prevent a penetration of moisture into an internal circuit. The moisture from a bonding pad to the internal circuit is blocked by providing an underlying polysilicon film (10) formed as a lower layer of a bonding pad, a bonding pad (1) formed above the underlying polysilicon film (10) through intermediation of an inter-layer insulation film (21), and an outer circumferential interconnecting line (3) formed so as to surround an outer side of the bonding pad 1, and by connecting the outer circumferential interconnecting line (3) and the underlying polysilicon film (10) with a continuous outer circumferential contact.

摘要翻译： 提供了一种被配置为防止湿气渗入内部电路的半导体器件。 通过提供形成为焊盘的下层的下面的多晶硅膜（10），通过形成在下面的多晶硅膜（10）上方的接合焊盘（1），从而将焊接焊盘到内部电路的水分阻挡 层间绝缘膜（21）和形成为包围接合焊盘1的外侧的外周互连线（3），并且通过连接外周互连线（3）和下面的多晶硅膜（10） ）具有连续的外圆周接触。

公开(公告)号：US20100105200A1

公开(公告)日：2010-04-29

申请号：US12651758

申请日：2010-01-04

申请人： Yaojian Lin ,  Xu-Sheng Bao

发明人： Yaojian Lin ,  Xu-Sheng Bao

IPC分类号： H01L21/60

CPC分类号： H05K3/3452 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02123 ,  H01L2224/02163 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13011 ,  H01L2224/13016 ,  H01L2224/131 ,  H01L2224/1613 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K1/112 ,  H05K3/3436 ,  H05K3/3457 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/099 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/014

摘要： A flip chip style semiconductor package has a substrate with a plurality of active devices formed thereon. A contact pad is formed over the substrate. An under bump metallization (UBM) layer is in electrical contact with the contact pad. A passivation layer is formed over the substrate. In one case, the UBM layer is disposed above the passivation layer. Alternatively, the passivation layer is disposed above the UBM layer. A portion of the passivation layer is removed to create a passivation island. The passivation island is centered with respect to the contact pad with its top surface devoid of the UBM layer. A solder bump is formed over the passivation island in electrical contact with the UBM layer. The passivation island forms a void in the solder bump for stress relief. The UBM layer may include a redistribution layer such that the passivation island is offset from the contact pad.

摘要翻译： 倒装片式半导体封装具有在其上形成有多个有源器件的衬底。 接触垫形成在衬底上。 凸块下金属化（UBM）层与接触焊盘电接触。 钝化层形成在衬底上。 在一种情况下，UBM层设置在钝化层上方。 或者，钝化层设置在UBM层上。 去除钝化层的一部分以产生钝化岛。 钝化岛相对于接触焊盘居中，其顶表面不含UBM层。 在与UBM层电接触的钝化岛上形成焊料凸点。 钝化岛在焊料凸块中形成空隙以消除应力。 UBM层可以包括再分布层，使得钝化岛从接触垫偏移。

公开(公告)号：US07667335B2

公开(公告)日：2010-02-23

申请号：US11858749

申请日：2007-09-20

申请人： Yaojian Lin ,  Xu Sheng Bao

发明人： Yaojian Lin ,  Xu Sheng Bao

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K3/3452 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02123 ,  H01L2224/02163 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13011 ,  H01L2224/13016 ,  H01L2224/131 ,  H01L2224/1613 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K1/112 ,  H05K3/3436 ,  H05K3/3457 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/099 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/014

摘要： A flip chip style semiconductor package has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate. An under bump metallization (UBM) layer is in electrical contact with the contact pad. A passivation layer is formed over the substrate. In one case, the UBM layer is disposed above the passivation layer. Alternatively, the passivation layer is disposed above the UBM layer. A portion of the passivation layer is removed to create a passivation island. The passivation island is centered with respect to the contact pad with its top surface devoid of the UBM layer. A solder bump is formed over the passivation island in electrical contact with the UBM layer. The passivation island forms a void in the solder bump for stress relief. The UBM layer may include a redistribution layer such that the passivation island is offset from the contact pad.

摘要翻译： 倒装片式半导体封装具有在其上形成有多个有源器件的衬底。 在基板上形成接触垫。 凸块下金属化（UBM）层与接触焊盘电接触。 钝化层形成在衬底上。 在一种情况下，UBM层设置在钝化层上方。 或者，钝化层设置在UBM层上。 去除钝化层的一部分以产生钝化岛。 钝化岛相对于接触焊盘居中，其顶表面没有UBM层。 在与UBM层电接触的钝化岛上形成焊料凸点。 钝化岛在焊料凸块中形成空隙以消除应力。 UBM层可以包括再分布层，使得钝化岛从接触垫偏移。

公开(公告)号：US11894247B2

公开(公告)日：2024-02-06

申请号：US17520556

申请日：2021-11-05

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Hsih-Yang Chiu

IPC分类号： H01L21/67 ,  H01L23/528 ,  H01L23/00

CPC分类号： H01L21/67121 ,  H01L21/67063 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/80 ,  H01L2224/02163 ,  H01L2224/0361 ,  H01L2224/08145 ,  H01L2224/80004

摘要： The present disclosure provides a mothed of method of manufacturing a semiconductor device. The method includes steps of forming a dielectric layer on a substrate; etching the dielectric layer to create a plurality of openings in the dielectric layer; applying a sacrificial layer in at least one of the openings to cover at least a portion of the dielectric layer; forming at least one first conductive feature in the openings where the sacrificial layer is disposed and a plurality of bases in the openings where the sacrificial layer is not disposed; removing the sacrificial layer to form at least one air gap in the dielectric layer; and forming a plurality of protrusions on the bases.

公开(公告)号：US20140361430A1

公开(公告)日：2014-12-11

申请号：US14287023

申请日：2014-05-24

申请人： Renesas Electronics Corporation

发明人： Yoshihiro Ono ,  Tsuyoshi Kida ,  Kenji Sakata

IPC分类号： H01L23/498

CPC分类号： H01L24/06 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02163 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05666 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13155 ,  H01L2224/14104 ,  H01L2224/14164 ,  H01L2224/14179 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/325 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014

摘要： A semiconductor chip and a wiring board are coupled to each other through conductor posts. The centers of conductor posts situated above openings at the outermost periphery shift from the centers of the openings in a direction away from the center of the semiconductor chip. When a region where each of the conductor posts and an insulating layer are overlapped with each other is designated as an overlapped region, the width of the overlapped region more on the inner side than the opening is smaller than the width of the overlapped region more on the outer side than the opening. Thus, while stress applied to the conductor posts is relaxed, coupling reliability between the semiconductor chip and the wiring board is retained.

摘要翻译： 半导体芯片和布线板通过导体柱彼此耦合。 位于最外周的开口上方的导体柱的中心在远离半导体芯片的中心的方向上从开口的中心偏移。 当每个导体柱和绝缘层彼此重叠的区域被指定为重叠区域时，内侧上比开口更多的重叠区域的宽度小于重叠区域的宽度 外侧比开口。 因此，在施加到导体柱的应力松弛的同时，保持了半导体芯片和布线板之间的耦合可靠性。