公开(公告)号：US09373597B2

公开(公告)日：2016-06-21

申请号：US14662151

申请日：2015-03-18

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Chia-Ming Cheng ,  Shu-Ming Chang

IPC: H01L23/00 ,  H01L29/06 ,  H01L23/525

CPC classification number: H01L24/14 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L29/0657 ,  H01L2224/02233 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/0236 ,  H01L2224/0237 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/14155 ,  H01L2224/14165 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/00014

Abstract: The present invention provides a chip package that includes a semiconductor chip, at least one recess, a plurality of first redistribution metal lines, and at least one protrusion. The semiconductor chip has a plurality of conductive pads disposed on an upper surface of the semiconductor chip. The recess extends from the upper surface to a lower surface of the semiconductor chip, and is arranged on the side of the semiconductor chip. The first redistribution metal lines are disposed on the upper surface, electrically connected to the conductive pad individually, and extended into the recesses separately. The protrusion is disposed in the recess and located between the adjacent first redistribution metal lines.

Abstract translation: 本发明提供了一种芯片封装，其包括半导体芯片，至少一个凹槽，多个第一再分布金属线以及至少一个突起。 半导体芯片具有设置在半导体芯片的上表面上的多个导电焊盘。 凹部从半导体芯片的上表面延伸到下表面，并且布置在半导体芯片的侧面上。 第一再分布金属线设置在上表面上，分别电连接到导电垫，并分别延伸到凹槽中。 突出部设置在凹部中并且位于相邻的第一再分布金属线之间。

公开(公告)号：US09111951B2

公开(公告)日：2015-08-18

申请号：US14172229

申请日：2014-02-04

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Keisuke Uemura ,  Jun Osanai

IPC: H01L23/04 ,  H01L23/00 ,  H01L23/48 ,  H01L23/29

CPC classification number: H01L23/564 ,  H01L23/293 ,  H01L23/481 ,  H01L24/05 ,  H01L2224/02163 ,  H01L2224/02233 ,  H01L2224/02255 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/00014

Abstract: Provided is a semiconductor device configured to prevent a penetration of moisture into an internal circuit. The moisture from a bonding pad to the internal circuit is blocked by providing an underlying polysilicon film (10) formed as a lower layer of a bonding pad, a bonding pad (1) formed above the underlying polysilicon film (10) through intermediation of an inter-layer insulation film (21), and an outer circumferential interconnecting line (3) formed so as to surround an outer side of the bonding pad 1, and by connecting the outer circumferential interconnecting line (3) and the underlying polysilicon film (10) with a continuous outer circumferential contact.

Abstract translation: 提供了一种被配置为防止湿气渗入内部电路的半导体器件。 通过提供形成为焊盘的下层的下面的多晶硅膜（10），通过形成在下面的多晶硅膜（10）上方的接合焊盘（1），从而将焊接焊盘到内部电路的水分阻挡 层间绝缘膜（21）和形成为包围接合焊盘1的外侧的外周互连线（3），并且通过连接外周互连线（3）和下面的多晶硅膜（10） ）具有连续的外圆周接触。

公开(公告)号：US20240128218A1

公开(公告)日：2024-04-18

申请号：US18156414

申请日：2023-01-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Pin Chang ,  Wei-Cheng Wu ,  Ming-Shih Yeh ,  An-Jhih Su ,  Der-Chyang Yeh

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L23/3171 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/16 ,  H01L24/24 ,  H01L2224/02233 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/06132 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13021 ,  H01L2224/16147 ,  H01L2224/24146

Abstract: A semiconductor package includes a first semiconductor substrate, an array of conductive bumps, a second semiconductor substrate, and a spacing pattern. The first semiconductor substrate includes a pad region and an array of first pads disposed within the pad region. The array of conductive bumps is disposed on the array of first pads respectively. The second semiconductor substrate is disposed over the first semiconductor substrate and includes an array of second pads bonded to the array of conductive bumps respectively. The spacing pattern is disposed between the first semiconductor substrate and the second semiconductor substrate, wherein the spacing pattern is located at a periphery of the pad region.

公开(公告)号：US20140217594A1

公开(公告)日：2014-08-07

申请号：US14172229

申请日：2014-02-04

Applicant: Seiko Instruments Inc.

Inventor： Keisuke UEMURA ,  Jun OSANAI

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L23/564 ,  H01L23/293 ,  H01L23/481 ,  H01L24/05 ,  H01L2224/02163 ,  H01L2224/02233 ,  H01L2224/02255 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/00014

Abstract: Provided is a semiconductor device configured to prevent a penetration of moisture into an internal circuit. The moisture from a bonding pad to the internal circuit is blocked by providing an underlying polysilicon film (10) formed as a lower layer of a bonding pad, a bonding pad (1) formed above the underlying polysilicon film (10) through intermediation of an inter-layer insulation film (21), and an outer circumferential interconnecting line (3) formed so as to surround an outer side of the bonding pad 1, and by connecting the outer circumferential interconnecting line (3) and the underlying polysilicon film (10) with a continuous outer circumferential contact.

Abstract translation: 提供了一种被配置为防止湿气渗入内部电路的半导体器件。 通过提供形成为焊盘的下层的下面的多晶硅膜（10），通过形成在下面的多晶硅膜（10）上方的接合焊盘（1），从而将焊接焊盘到内部电路的水分阻挡 层间绝缘膜（21）和形成为包围接合焊盘1的外侧的外周互连线（3），并且通过连接外周互连线（3）和下面的多晶硅膜（10） ）具有连续的外圆周接触。

公开(公告)号：US08647974B2

公开(公告)日：2014-02-11

申请号：US13072554

申请日：2011-03-25

Applicant: Roden R. Topacio ,  Michael Z. Su ,  Neil McLellan

Inventor： Roden R. Topacio ,  Michael Z. Su ,  Neil McLellan

IPC: H01L21/44 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02233 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/13111 ,  H01L2224/73204 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip that has a first conductor pad and a passivation structure. A second conductor pad is fabricated around but not in physical contact with the first conductor pad to leave a gap. The second conductor pad is adapted to protect a portion of the passivation structure.

Abstract translation: 公开了各种半导体芯片输入/输出结构及其制造方法。 一方面，提供一种制造方法，其包括提供具有第一导体焊盘和钝化结构的半导体芯片。 围绕第二导体焊盘制造第二导体焊盘而不与第一导体焊盘物理接触以留下间隙。 第二导体焊盘适于保护钝化结构的一部分。

公开(公告)号：US08421208B2

公开(公告)日：2013-04-16

申请号：US13221037

申请日：2011-08-30

Applicant: Kouji Takemura

Inventor： Kouji Takemura

IPC: H01L23/48 ,  H01L21/44 ,  H05K7/10

CPC classification number: H01L23/3171 ,  H01L22/32 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/02233 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a semiconductor integrated circuit device (1). In the semiconductor integrated circuit device (1), a semiconductor integrated circuit (5) is formed on a center of the surface of a semiconductor substrate (3), and a plurality of electrode terminals (71, 73, . . . ) are provided on the surface of the semiconductor substrate (3). A protection film (9) is provided on the surface of the semiconductor substrate (3) such that the surfaces of the electrode terminals (71, 73) are exposed. The electrode terminals (71, 73, . . . ) include an electrode terminal (73) having a thin portion (74). The surface of the thin portion (74) is located below the surfaces of the electrode terminals except for the electrode terminal (73) having the thin portion (74) among the electrode terminals (71, 73, . . . ).

Abstract translation: 半导体器件包括半导体集成电路器件（1）。 在半导体集成电路器件（1）中，半导体集成电路（5）形成在半导体衬底（3）的表面的中心，并且提供多个电极端子（71,73） 在半导体衬底（3）的表面上。 在半导体基板（3）的表面上设置保护膜（9），使得电极端子（71,73）的表面露出。 电极端子（71,73 ...）包括具有薄部分（74）的电极端子（73）。 除了在电极端子（71,73 ...中）中具有薄部分（74）的电极端子（73）之外，薄部分（74）的表面位于电极端子的表面下方。

公开(公告)号：US08143693B2

公开(公告)日：2012-03-27

申请号：US12098352

申请日：2008-04-04

Applicant: Seung-Duk Baek ,  Sun-Won Kang ,  Hyun-Soo Chung

Inventor： Seung-Duk Baek ,  Sun-Won Kang ,  Hyun-Soo Chung

IPC: H01L29/00

CPC classification number: H01L23/525 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/02 ,  H01L2224/02233 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/181 ,  H01L2924/00

Abstract: The invention provides a semiconductor device. The semiconductor device includes a semiconductor chip having an active surface on which pads are disposed, a passivation layer pattern disposed to cover the active surface of the semiconductor chip and to expose the pads, a first insulation layer pattern disposed on the passivation layer pattern, a second insulation layer pattern disposed on only a portion of the first insulation layer pattern, and redistribution line patterns electrically connected to the pads and disposed so as to extend across the second insulation layer pattern and the first insulation layer pattern. A method of fabricating the same is also provided.

Abstract translation: 本发明提供一种半导体器件。 半导体器件包括具有布置有焊盘的有源表面的半导体芯片，布置成覆盖半导体芯片的有源表面并暴露焊盘的钝化层图案，设置在钝化层图案上的第一绝缘层图案， 第二绝缘层图案仅设置在第一绝缘层图案的一部分上，再分布线图形电连接到焊盘并且被设置成跨越第二绝缘层图案和第一绝缘层图案延伸。 还提供了一种制造该方法的方法。

公开(公告)号：US20150270236A1

公开(公告)日：2015-09-24

申请号：US14662151

申请日：2015-03-18

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Chia-Ming CHENG ,  Shu-Ming CHANG

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L29/0657 ,  H01L2224/02233 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/0236 ,  H01L2224/0237 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/14155 ,  H01L2224/14165 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/00014

Abstract: The present invention provides a chip package that includes a semiconductor chip, at least one recess, a plurality of first redistribution metal lines, and at least one protrusion. The semiconductor chip has a plurality of conductive pads disposed on an upper surface of the semiconductor chip. The recess extends from the upper surface to a lower surface of the semiconductor chip, and is arranged on the side of the semiconductor chip. The first redistribution metal lines are disposed on the upper surface, electrically connected to the conductive pad individually, and extended into the recesses separately. The protrusion is disposed in the recess and located between the adjacent first redistribution metal lines.

Abstract translation: 本发明提供了一种芯片封装，其包括半导体芯片，至少一个凹槽，多个第一再分布金属线以及至少一个突起。 半导体芯片具有设置在半导体芯片的上表面上的多个导电焊盘。 凹部从半导体芯片的上表面延伸到下表面，并且布置在半导体芯片的侧面上。 第一再分布金属线设置在上表面上，分别电连接到导电垫，并分别延伸到凹槽中。 突出部设置在凹部中并且位于相邻的第一再分布金属线之间。

公开(公告)号：US20130307119A1

公开(公告)日：2013-11-21

申请号：US13536877

申请日：2012-06-28

Applicant: Shuo-Mao CHEN ,  Der-Chyang YEH ,  Chiung-Han YEH

Inventor： Shuo-Mao CHEN ,  Der-Chyang YEH ,  Chiung-Han YEH

IPC: H01L27/06

CPC classification number: H01L23/49822 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/19 ,  H01L2224/02233 ,  H01L2224/02331 ,  H01L2224/02381 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05099 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06515 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2924/01047 ,  H01L2924/00

Abstract: A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.

Abstract translation: 包装包括形成在包装的第一区域中的碎屑和形成在包装件的与第一区域相邻的第二区域中的模塑料。 在芯片和模塑料上形成第一聚合物层，在第一聚合物层上形成第二聚合物层，并且在第一聚合物层和第二聚合物层之间形成多个互连结构。 金属 - 绝缘体 - 金属（MIM）电容器形成在第二聚合物层上并电耦合到多个互连结构中的至少一个。 金属凸块形成在多个互连结构中的至少一个互连结构上并电耦合到多个互连结构中。

公开(公告)号：US20120241985A1

公开(公告)日：2012-09-27

申请号：US13072554

申请日：2011-03-25

Applicant: Roden R. Topacio ,  Michael Z. Su ,  Neil McLellan

Inventor： Roden R. Topacio ,  Michael Z. Su ,  Neil McLellan

IPC: H01L23/488 ,  H01L21/58 ,  H01L21/28

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02233 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/13111 ,  H01L2224/73204 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip that has a first conductor pad and a passivation structure. A second conductor pad is fabricated around but not in physical contact with the first conductor pad to leave a gap. The second conductor pad is adapted to protect a portion of the passivation structure.

Abstract translation: 公开了各种半导体芯片输入/输出结构及其制造方法。 一方面，提供一种制造方法，其包括提供具有第一导体焊盘和钝化结构的半导体芯片。 围绕第二导体焊盘制造第二导体焊盘而不与第一导体焊盘物理接触以留下间隙。 第二导体焊盘适于保护钝化结构的一部分。