公开(公告)号：US20130307119A1

公开(公告)日：2013-11-21

申请号：US13536877

申请日：2012-06-28

Applicant: Shuo-Mao CHEN ,  Der-Chyang YEH ,  Chiung-Han YEH

Inventor： Shuo-Mao CHEN ,  Der-Chyang YEH ,  Chiung-Han YEH

IPC: H01L27/06

CPC classification number: H01L23/49822 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/19 ,  H01L2224/02233 ,  H01L2224/02331 ,  H01L2224/02381 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05099 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06515 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2924/01047 ,  H01L2924/00

Abstract: A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.

Abstract translation: 包装包括形成在包装的第一区域中的碎屑和形成在包装件的与第一区域相邻的第二区域中的模塑料。 在芯片和模塑料上形成第一聚合物层，在第一聚合物层上形成第二聚合物层，并且在第一聚合物层和第二聚合物层之间形成多个互连结构。 金属 - 绝缘体 - 金属（MIM）电容器形成在第二聚合物层上并电耦合到多个互连结构中的至少一个。 金属凸块形成在多个互连结构中的至少一个互连结构上并电耦合到多个互连结构中。

公开(公告)号：US20130043541A1

公开(公告)日：2013-02-21

申请号：US13546024

申请日：2012-07-11

Applicant: Chung-Hui CHEN ,  Jaw-Juinn HORNG ,  Shuo-Mao CHEN ,  Der-Chyang YEH

Inventor： Chung-Hui CHEN ,  Jaw-Juinn HORNG ,  Shuo-Mao CHEN ,  Der-Chyang YEH

IPC: H01L23/48 ,  H01L29/78

CPC classification number: H01L25/0657 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L2225/06572 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A TSV interface circuit for a TSV provided in an interposer substrate that forms a connection between a first die and a second die includes a driving circuit provided in the first die and a receiver circuit provided in the second die where the driving circuit is coupled to a first supply voltage and a second supply voltage that are both lower than the interposer substrate voltage that substantially reduces the parasitic capacitance of the TSV. The receiver circuit is also coupled to the first supply voltage and the second supply voltage that are both lower than the interposer substrate voltage.

Abstract translation: 设置在形成第一管芯和第二管芯之间的连接的插入器基板中的TSV的TSV接口电路包括设置在第一管芯中的驱动电路和设置在第二管芯中的接收器电路，其中驱动电路耦合到 第一电源电压和第二电源电压均低于基本上降低TSV的寄生电容的插入器基板电压。 接收器电路还耦合到低于插入器基板电压的第一电源电压和第二电源电压。