-
公开(公告)号:US11807522B2
公开(公告)日:2023-11-07
申请号:US16927648
申请日:2020-07-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Jane Qian Liu , Gary Philip Thomson , Richard Allen Richter
CPC classification number: B81C1/00896 , B81B7/0067 , B81C1/00317 , G02B27/0006 , B81B2201/042 , B81C2203/019 , G02B26/0833
Abstract: In described examples, a device mounted on a substrate includes an encapsulant. In at least one example, an encapsulant barrier is deposited along a scribe line, along which the substrate is singulatable. To encapsulate one or more terminals of the substrate, an encapsulant is deposited between the encapsulant barrier and an edge of the device parallel to the encapsulant barrier.
-
公开(公告)号:US20230324678A1
公开(公告)日:2023-10-12
申请号:US18206363
申请日:2023-06-06
Applicant: STMicroelectronics S.r.l.
Inventor: Giorgio ALLEGATO , Sonia COSTANTINI , Federico VERCESI , Roberto CARMINATI
CPC classification number: G02B26/105 , B81C1/00317 , G02B26/0833 , B81C2203/0109 , B81B2201/042 , B81C2203/019 , B81C1/00523
Abstract: A method of making a MEMS device including forming a mirror stack on a handle layer, applying a first bonding layer to the mirror stack, and disposing a substrate on the first bonding layer. The handle layer is removed and a second bonding layer is applied. A cap layer is disposed on the second bonding layer. The mirror stack is formed by disposing a silicon layer on the handle layer, disposing a first insulating layer on the silicon layer, etching portions of the first insulating layer, and depositing a first conductive layer on the first insulating layer. The formation also includes depositing a second insulating layer on the first conductive layer, a portion of the second insulating layer to expose a portion of the first conductive layer exposed, and forming a conductive pad on the exposed portion of the first conductive layer.
-
公开(公告)号:US11760059B2
公开(公告)日:2023-09-19
申请号:US16521493
申请日:2019-07-24
Applicant: INVENSAS BONDING TECHNOLOGIES, INC.
Inventor: Qin-Yi Tong
IPC: B32B7/04 , B81C1/00 , H01L21/3105 , H01L21/762 , H01L23/00
CPC classification number: B32B7/04 , B81C1/00357 , H01L21/3105 , H01L21/76251 , H01L24/26 , H01L24/29 , H01L24/81 , H01L24/83 , H01L24/92 , B32B2250/04 , B81C2201/019 , B81C2203/019 , B81C2203/0118 , H01L2224/0401 , H01L2224/08059 , H01L2224/29186 , H01L2224/80896 , H01L2224/81894 , H01L2224/81895 , H01L2224/8319 , H01L2224/8385 , H01L2224/83894 , H01L2224/83896 , H01L2224/9202 , H01L2224/9212 , H01L2224/92125 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01016 , H01L2924/01018 , H01L2924/01019 , H01L2924/01023 , H01L2924/01033 , H01L2924/01039 , H01L2924/01058 , H01L2924/01067 , H01L2924/01072 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/07802 , H01L2924/10253 , H01L2924/1305 , H01L2924/14 , H01L2924/1461 , H01L2924/351 , Y10T156/10 , Y10T428/24355 , Y10T428/24942 , Y10T428/31504 , Y10T428/31678 , H01L2924/3512 , H01L2924/00 , H01L2924/10253 , H01L2924/00 , H01L2224/29186 , H01L2924/05442 , H01L2224/9212 , H01L2224/81895 , H01L2224/80896 , H01L2924/1461 , H01L2924/00 , H01L2924/1305 , H01L2924/00 , H01L2924/351 , H01L2924/00
Abstract: A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH2 species. This may be accomplished by exposing the bonding layer to an NH4OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.
-
公开(公告)号:US11707230B2
公开(公告)日:2023-07-25
申请号:US16298356
申请日:2019-03-11
Applicant: ENDOTRONIX, INC.
Inventor: Harry Rowland , Michael Nagy , Balamurugan Sundaram , Suresh Sundaram
IPC: B81C1/00 , A61B5/00 , A61B5/0215 , A61B5/07 , G01L19/06 , G01L9/00 , H05K9/00 , B81B3/00 , G01L19/00
CPC classification number: A61B5/686 , A61B5/0215 , A61B5/076 , B81B3/0035 , B81C1/00261 , G01L9/0042 , G01L19/0038 , G01L19/0618 , H05K9/0024 , A61B2562/0247 , A61B2562/168 , B81B2201/0264 , B81C2203/0109 , B81C2203/019 , B81C2203/0118 , B81C2203/075 , H05K2201/10151 , H05K2201/10371
Abstract: A wireless circuit includes a housing having at least one opening, and sensor connected to the housing at the opening. The sensor includes a first layer having a first dimension and a second layer having a second dimension shorter than the first dimension. The second layer may be positioned entirely within the housing and a surface of said first layer may be exposed to an exterior of the housing.
-
5.
公开(公告)号:US20180215610A1
公开(公告)日:2018-08-02
申请号:US15928008
申请日:2018-03-21
Applicant: ULIS
Inventor: Jérôme Favier , David Bunel
CPC classification number: B81B7/0038 , B81B2201/0207 , B81C1/00269 , B81C1/00285 , B81C2203/0145 , B81C2203/019 , G01J5/20 , H01L23/564 , H01L31/186 , H01L2224/48091 , H01L2924/00014
Abstract: A device having a microelectronic component housed in a hermetically sealed housing having a vacuum inner space, and including a getter that substantially traps only hydrogen, is inert to oxygen and/or to nitrogen, and is housed in said inner space. Each of the constituent parts of the device being likely to degas into the inner space is a mineral material.
-
公开(公告)号:US09975757B2
公开(公告)日:2018-05-22
申请号:US14729456
申请日:2015-06-03
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Lee-Chuan Tseng , Chung-Yen Chou , Shih-Chang Liu , Yuan-Chih Hsieh
CPC classification number: B81B7/0041 , B81B2201/0235 , B81B2201/0257 , B81B2201/0264 , B81B2207/012 , B81C1/00293 , B81C3/001 , B81C2203/0109 , B81C2203/0145 , B81C2203/019
Abstract: A microelectromechanical systems (MEMS) structure with a cavity hermetically sealed using a mask layer is provided. A capping substrate is arranged over a MEMS substrate, which includes a movable element. The capping substrate includes the cavity arranged over and opening to the movable element, and includes a seal opening in fluid communication with the cavity. The mask layer is arranged over the capping substrate. The mask layer overhangs the seal opening and laterally surrounds a mask opening arranged over the seal opening. A seal layer is arranged over the mask layer and the mask opening. The seal layer is configured to hermetically seal the cavity. A method for manufacturing the MEMS structure is also provided.
-
公开(公告)号:US09969610B2
公开(公告)日:2018-05-15
申请号:US15416206
申请日:2017-01-26
Applicant: Raytheon Company
Inventor: Buu Q. Diep , Adam M. Kennedy , Thomas Allan Kocian , Mark Lamb
IPC: H01L31/0203 , B81B7/00 , B81C1/00
CPC classification number: B81B7/0058 , B81B7/0041 , B81B2201/0207 , B81B2201/04 , B81C1/00269 , B81C1/00317 , B81C2203/0109 , B81C2203/0118 , B81C2203/0145 , B81C2203/019
Abstract: A microelectromechanical systems (MEMS) package includes a substrate extending between a first pair of outer edges to define a length and a second pair of outer edges to define a width. A seal ring assembly is disposed on the substrate and includes at least one seal ring creating a first boundary point adjacent to at least one MEMS device and a second boundary point adjacent at least one of the outer edges. The package further includes a window lid on the seal ring assembly to define a seal gap containing the at least one MEMS device. The seal ring assembly anchors the window lid to the substrate at the second boundary point such that deflection of the window lid into the seal gap is reduced.
-
公开(公告)号:US09932221B1
公开(公告)日:2018-04-03
申请号:US15448177
申请日:2017-03-02
Applicant: Amkor Technology, Inc.
Inventor: Lawrence Prestousa Natan , Adrian Arcedera , Roveluz Lledo-Reyes , Sarah Christine-Sanchez Torrefranca
CPC classification number: B81B7/0074 , B81B2201/0257 , B81B2203/0127 , B81B2203/0315 , B81B2207/07 , B81B2207/097 , B81C1/00333 , B81C2203/019
Abstract: A semiconductor device may include a first substrate, a first electrical component, a lid, a second substrate, and a second electrical component. The first substrate may include an upper surface, a lower surface, and an upper cavity in the upper surface. The first electrical component may reside in the upper cavity of the first substrate. The lid may cover the upper cavity and may include a port that permits fluid to flow between an environment external to the semiconductor device and the upper cavity. The second substrate may include the second electrical component mounted to an upper surface of the second substrate. The lower surface of the first substrate and the upper surface of the second substrate may fluidically seal the second electrical component from the upper cavity.
-
公开(公告)号:US20180059405A1
公开(公告)日:2018-03-01
申请号:US15245805
申请日:2016-08-24
Applicant: STMicroelectronics S.r.l.
Inventor: Giorgio Allegato , Sonia Costantini , Federico Vercesi , Roberto Carminati
CPC classification number: G02B26/105 , B81B2201/042 , B81C1/00317 , B81C2203/0109 , B81C2203/019 , G02B26/0833
Abstract: Disclosed herein is a micro-electro mechanical (MEMS) device including a substrate, and a MEMS mirror stack on the substrate. A first bonding layer seals against ingress of environmental contaminants and mechanically anchors the MEMS mirror stack to the substrate. A cap layer is formed on the MEMS mirror stack. A second boding layer seals against ingress of environmental contaminants and mechanically anchors the cap layer to the MEMS mirror stack.
-
公开(公告)号:US20180044175A1
公开(公告)日:2018-02-15
申请号:US15556161
申请日:2015-08-18
Applicant: TANAKA KIKINZOKU KOGYO K.K.
Inventor: Toshinori OGASHIWA , Yuya SASAKI , Masayuki MIYAIRI
IPC: B81C1/00
CPC classification number: B81C1/00269 , B81C3/00 , B81C2203/0118 , B81C2203/019 , B81C2203/036 , H01L23/02
Abstract: The present invention relates to a package production method includes the step of superposing a pair of substrates on each other, and bonding the substrates to each other to hermetically seal the inside of a sealing region surrounded by a sealing material, which is formed on any of the substrates. The sealing material is formed of a sintered body obtained by sintering a metal powder of at least one selected from gold, silver, palladium and platinum, the metal powder having a purity of 99.9% by weight or more and an average particle size of 0.005 μm to 1.0 μm, at least one core material having a width smaller than the width of the sealing material in a cross-sectional shape, and protruding from the periphery is formed on the substrate, and the core material compresses the sealing material to exhibit a sealing effect when the pair of substrates are bonded to each other. Accordingly, a sufficient sealing effect can be exhibited while a pressuring force to the substrate is reduced.
-
-
-
-
-
-
-
-
-