公开(公告)号：US20180166351A1

公开(公告)日：2018-06-14

申请号：US15616908

申请日：2017-06-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ying-Shin HAN ,  Yen-Miao LIN ,  Chung-Chih CHEN ,  Hsien-Liang MENG

IPC: H01L23/10 ,  H01L21/48 ,  H01L23/053 ,  H01L23/00

CPC classification number: H01L23/10 ,  H01L21/4817 ,  H01L23/053 ,  H01L23/145 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/42 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2924/16251 ,  H01L2924/163 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00

Abstract: A semiconductor package includes a substrate, an integrated circuit die, a lid and an adhesive. The integrated circuit die is disposed over the substrate. The lid is disposed over the substrate. The lid includes a cap portion and a foot portion extending from a bottom surface of the cap portion. The cap portion and the foot portion define a recess, and the integrated circuit die is accommodated in the recess. The adhesive includes a sidewall portion and a bottom portion. The sidewall portion contacts a sidewall of the foot portion. The bottom portion extends from the sidewall portion to between a bottom surface of the foot portion and the substrate.

公开(公告)号：US20180158794A1

公开(公告)日：2018-06-07

申请号：US15575522

申请日：2016-06-01

Applicant: Mitsubishi Electric Corporation

Inventor： Kiyoshi ISHIDA ,  Makoto KIMURA ,  Katsumi MIYAWAKI ,  Yukinobu TARUI ,  Keiko SHIRAFUJI

IPC: H01L23/00 ,  H01L23/04

CPC classification number: H01L24/48 ,  H01L21/50 ,  H01L23/04 ,  H01L23/055 ,  H01L23/10 ,  H01L24/73 ,  H01L2224/4807 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/16152 ,  H01L2924/163 ,  H01L2924/1631 ,  H01L2924/3025 ,  H01L2224/45099

Abstract: A semiconductor device includes a substrate, a semiconductor element, a ground pad, an insulating coating member, a conductive bonding member, and a conductive cap. The inner peripheral end of a bottom of the conductive cap is disposed at a side close to the inner periphery of the insulating coating member relative to the outer peripheral end of the insulating coating member. The bottom has a shape in which the distance between the main surface and itself decreases continuously from its outer peripheral end toward its inner peripheral end.

公开(公告)号：US20170170030A1

公开(公告)日：2017-06-15

申请号：US14964256

申请日：2015-12-09

Applicant: International Business Machines Corporation

Inventor： Sushumna Iruvanti ,  Shidong Li ,  Kamal K. Sikka ,  Hilton T. Toy ,  Jeffrey A. Zitz

IPC: H01L21/56 ,  H01L21/48

CPC classification number: H01L21/56 ,  H01L21/4817 ,  H01L21/4853 ,  H01L21/50 ,  H01L23/10 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/42 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/16195 ,  H01L2924/163 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An electronic package includes a carrier and a semiconductor chip. In a first aspect a lid is attached to the chip and subsequently the gap between the lid and the carrier is filled by a seal band that includes seal band material and a plurality of shim members. In another aspect, an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material. In another aspect, the lid includes a plurality of surfaces at different topographies to reduce the thickness of the seal band between the topographic lid and the carrier. In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or elastomer and placed on the chip with a thermal interface material. The seal band material is dispensed on the chip carrier and the frame is then moved towards the chip carrier allowing a minimum seal band thickness.

公开(公告)号：US09653312B2

公开(公告)日：2017-05-16

申请号：US14559197

申请日：2014-12-03

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation

Inventor： Yuankun Hou ,  Kuanchieh Yu ,  Yu Hua ,  Yuelin Zhao

IPC: H01L23/544 ,  H01L21/308 ,  H01L25/00 ,  H01L23/10 ,  H01L23/00 ,  H01L21/66

CPC classification number: H01L21/56 ,  H01L21/30604 ,  H01L21/308 ,  H01L22/12 ,  H01L23/10 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/05571 ,  H01L2224/0612 ,  H01L2224/08145 ,  H01L2224/08148 ,  H01L2224/2761 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/29014 ,  H01L2224/29078 ,  H01L2224/30145 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/80011 ,  H01L2224/80203 ,  H01L2224/80805 ,  H01L2224/8081 ,  H01L2224/80895 ,  H01L2224/83011 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83805 ,  H01L2224/8381 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/00015 ,  H01L2924/0002 ,  H01L2924/163 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/2919 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/80

Abstract: A method of forming a sealing structure for a bonded wafer is provided. The method includes providing the lower wafer and the upper wafer, forming a sealing material layer on each of the lower wafer and the upper wafer, forming a mask layer on the sealing material layer on each of the lower wafer and the upper wafer, etching the sealing material layer using the mask layer as an etch mask, so as to form a first protrusion at an edge of the lower wafer and a second protrusion at an edge of the upper wafer, and bonding the first protrusion and the second protrusion together to form the sealing structure. The sealing structure encloses a gap between the lower wafer and the upper wafer at an edge of the bonded wafer, so as to form a hermetically sealed cavity at the edge of the bonded wafer.

公开(公告)号：US09613926B2

公开(公告)日：2017-04-04

申请号：US14712729

申请日：2015-05-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Ming-Fa Chen ,  Wen-Ching Tsai

IPC: H01L23/00 ,  B81C3/00 ,  H01L23/10 ,  H01L21/50

CPC classification number: H01L24/81 ,  B81C1/00238 ,  B81C3/001 ,  B81C2203/031 ,  B81C2203/035 ,  H01L21/50 ,  H01L23/10 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03602 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05149 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/06051 ,  H01L2224/08225 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/119 ,  H01L2224/11912 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13149 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/16014 ,  H01L2224/16147 ,  H01L2224/2745 ,  H01L2224/27452 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/2747 ,  H01L2224/27614 ,  H01L2224/279 ,  H01L2224/27912 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29014 ,  H01L2224/29082 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29124 ,  H01L2224/29138 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29149 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/32014 ,  H01L2224/32147 ,  H01L2224/32225 ,  H01L2224/73103 ,  H01L2224/80805 ,  H01L2224/80893 ,  H01L2224/80894 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/83805 ,  H01L2224/83815 ,  H01L2224/8383 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2924/10158 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2924/00012 ,  H01L2224/0347 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/114 ,  H01L2224/1146 ,  H01L2224/1161 ,  H01L2224/274 ,  H01L2224/2746 ,  H01L2224/2761 ,  H01L21/302 ,  H01L2224/034 ,  H01L2224/0361 ,  H01L2224/80

Abstract: Bonded structures and method of forming the same are provided. A conductive layer is formed on a first surface of a bonded structure, the bonded structure including a first substrate bonded to a second substrate, the first surface of the bonded structure being an exposed surface of the first substrate. A patterned mask having first openings and second openings is formed on the conductive layer, the first openings and the second openings exposing portions of the conductive layer. First portions of first bonding connectors are formed in the first openings and first portions of second bonding connectors are formed in the second openings. The conductive layer is patterned to form second portions of the first bonding connectors and second portions of the second bonding connectors. The bonded structure is bonded to a third substrate using the first bonding connectors and the second bonding connectors.

公开(公告)号：US09385060B1

公开(公告)日：2016-07-05

申请号：US14341586

申请日：2014-07-25

Applicant: Altera Corporation

Inventor： Vincent Hool ,  Minghao Shen

IPC: H01L21/44 ,  H01L23/34 ,  H01L21/48 ,  H01L23/373

CPC classification number: H01L23/3736 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/36 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/163 ,  H01L2924/18161 ,  H01L2224/11

Abstract: Integrated circuit packages with enhanced thermal conduction are disclosed. A disclosed integrated circuit package includes a package substrate. An integrated circuit die with a layer of metal on its backside is mounted on the package substrate at a first temperature (e.g., reflow temperature). The package further includes a heat spreading lid that is bonded to the integrated circuit die at a second temperature, which is less than the first temperature. The heat spreading lid is formed over the integrated circuit die in which the heat spreading lid makes physical contact with the integrated circuit die via the layer of metal.

Abstract translation: 公开了具有增强的热传导的集成电路封装。 所公开的集成电路封装包括封装衬底。 在第一温度（例如回流温度）下，在封装衬底上安装具有金属背面的集成电路裸片。 该封装还包括散热盖，其在小于第一温度的第二温度下结合到集成电路管芯。 散热盖形成在集成电路管芯上，其中散热盖通过金属层与集成电路管芯物理接触。

公开(公告)号：US09187312B2

公开(公告)日：2015-11-17

申请号：US14202756

申请日：2014-03-10

Applicant: Raytheon Company

Inventor： Roland Gooch ,  Buu Diep ,  Thomas Allan Kocian ,  Stephen H. Black ,  Adam M. Kennedy

IPC: H01L21/30 ,  B81B7/00 ,  B81C1/00 ,  H01L23/053 ,  H01L23/00

CPC classification number: B81B7/0041 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/019 ,  H01L23/053 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27444 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/83001 ,  H01L2224/83007 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

公开(公告)号：US20150069597A1

公开(公告)日：2015-03-12

申请号：US14322216

申请日：2014-07-02

Applicant: Kabushiki Kaisha Toshiba

Inventor： Keiichi MATSUSHITA ,  Yo SASAKI

IPC: H01L23/373 ,  H01L23/00

CPC classification number: H01L23/3736 ,  H01L21/50 ,  H01L23/10 ,  H01L23/142 ,  H01L23/4827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/0346 ,  H01L2224/04026 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05647 ,  H01L2224/2741 ,  H01L2224/2743 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/29084 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/32245 ,  H01L2224/32501 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83359 ,  H01L2224/83379 ,  H01L2224/83447 ,  H01L2224/83825 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/161 ,  H01L2924/16195 ,  H01L2924/163 ,  H01L2924/171 ,  H01L2924/2064 ,  H01L2224/05644 ,  H01L2924/00012 ,  H01L2224/06164 ,  H01L2224/45099

Abstract: According to one embodiment, a semiconductor device includes a semiconductor element, a mounting member including Cu, and a bonding layer provided between the semiconductor element and the mounting member. The bonding layer includes a first region including Ti and Cu, and a second region provided between the first region and the mounting member, and including Sn and Cu. A first position along the first direction is positioned between the semiconductor element and a second position along the first direction. The first position is where the composition ratio of Ti in the first region is 0.1 times a maximum value of the composition ratio of Ti. The second position is where the composition ratio of Sn in the second region is 0.1 times a maximum value of the composition ratio of Sn. A distance between the first position and the second position is not less than 0.1 micrometers.

Abstract translation: 根据一个实施例，半导体器件包括半导体元件，包括Cu的安装构件和设置在半导体元件和安装构件之间的接合层。 接合层包括包括Ti和Cu的第一区域，以及设置在第一区域和安装构件之间的包括Sn和Cu的第二区域。 沿着第一方向的第一位置位于半导体元件和沿第一方向的第二位置之间。 第一位置是第一区域中的Ti的组成比为Ti的组成比的最大值的0.1倍。 第二位置是第二区域中的Sn的组成比为Sn的组成比的最大值的0.1倍。 第一位置和第二位置之间的距离不小于0.1微米。

公开(公告)号：US08907482B2

公开(公告)日：2014-12-09

申请号：US13672393

申请日：2012-11-08

Applicant: Honeywell International Inc.

Inventor： David Scheid

IPC: H01L23/31 ,  H01L23/532

CPC classification number: H01L24/82 ,  H01L23/053 ,  H01L23/10 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/2401 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24227 ,  H01L2224/245 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32237 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48105 ,  H01L2224/48229 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/82101 ,  H01L2224/82102 ,  H01L2224/82104 ,  H01L2224/8285 ,  H01L2224/82855 ,  H01L2224/82862 ,  H01L2224/82874 ,  H01L2224/82986 ,  H01L2224/852 ,  H01L2224/85205 ,  H01L2224/85801 ,  H01L2224/8592 ,  H01L2224/92137 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/163 ,  H01L2924/165 ,  H01L2924/1659 ,  H01L2924/00014 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2924/00012

Abstract: A system may include a package defining a cavity and an integrated circuit (IC) disposed within the cavity. The package may include a first electrically conductive package contact and a second electrically conductive package contact. The IC may include a first electrically conductive IC contact and a second electrically conductive IC contact. The system also may include a wire bond extending between and electrically connecting the first electrically conductive package contact and the first electrically conductive IC contact. The system further may include an electrically conductive adhesive extending between and electrically connecting the second electrically conductive package contact and the second electrically conductive IC contact. Use of wire bonds and electrically conductive adhesive may increase an interconnect density between the IC and the package, while not requiring an increase in size of the IC or a decrease in pitch between wire bonds.

Abstract translation: 系统可以包括限定空腔的封装和设置在腔内的集成电路（IC）。 封装可以包括第一导电封装触点和第二导电封装触点。 IC可以包括第一导电IC触点和第二导电IC触点。 该系统还可以包括在第一导电封装触点和第一导电IC触点之间延伸并电连接第一导电封装触点和第一导电IC触点之间的引线键合。 该系统还可以包括在第二导电封装触点和第二导电IC触点之间延伸并电连接第二导电封装触点和第二导电IC触点之间的导电粘合剂。 使用引线键合和导电粘合剂可以增加IC和封装之间的互连密度，而不需要IC的尺寸增加或引线键合之间的间距减小。

公开(公告)号：US08736045B1

公开(公告)日：2014-05-27

申请号：US13667458

申请日：2012-11-02

Applicant: Raytheon Company

Inventor： Roland Gooch ,  Buu Diep ,  Thomas Allan Kocian ,  Stephen H. Black ,  Allan M. Kennedy

IPC: H01L23/12

CPC classification number: B81B7/0041 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/019 ,  H01L23/053 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27444 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/83001 ,  H01L2224/83007 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

Abstract translation: 一种形成晶片级封装电路器件的方法包括形成器件晶片，器件晶片包括残留在器件晶片的衬底的第一区域中的第一组一个或多个材料层; 以及形成被配置为附接到所述器件晶片的盖晶片，所述盖晶片包括留在所述盖晶片的衬底的第二区域中的第二组一个或多个材料层; 其中一个或多个材料层的所述第一和第二组的组合厚度在所述器件晶片和所述盖晶片接合时限定了整合的接合间隙控制结构。