公开(公告)号：US11990458B2

公开(公告)日：2024-05-21

申请号：US17421684

申请日：2020-09-02

申请人： LG Display Co., Ltd.

发明人： Jae Yong Choi ,  Seung Jun Lee

IPC分类号： H01L25/16 ,  H01L23/00 ,  H01L27/12 ,  H01L33/62

CPC分类号： H01L25/167 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L33/62 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/24051 ,  H01L2224/24147 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/25174 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2924/0542 ,  H01L2924/0544 ,  H01L2924/0549 ,  H01L2924/12041 ,  H01L2933/0066

摘要： The present disclosure relates to an LED display device, and more particularly, to an LED display device including a repair structure for a deteriorated pixel. In the present disclosure, a sub LED electrically coupled to first and second connecting electrodes for applying a voltage to a LED is disposed on a deteriorated LED. Thus, deterioration of a display quality due to a deteriorated pixel is prevented. Since it is not required to remove a deteriorated LED, a fabrication cost is reduced and a process efficiency is improved.

公开(公告)号：US20240047288A1

公开(公告)日：2024-02-08

申请号：US17959314

申请日：2022-10-04

申请人： InnoLux Corporation

发明人： Sheng-Nan CHEN ,  Chia-Lin YANG ,  Kuan-Feng LEE ,  Jui-Jen YUEH

IPC分类号： H01L23/29 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31

CPC分类号： H01L23/293 ,  H01L24/24 ,  H01L24/19 ,  H01L24/16 ,  H01L23/49833 ,  H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L21/566 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/3142 ,  H01L23/3135 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/18301 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L23/3121 ,  H01L2924/186

摘要： The present disclosure provides an electronic device including a first electronic unit, a second electronic unit, a circuit layer, a protection layer, and a flexible member. The first electronic unit is electrically connected to the second electronic unit through the circuit layer. The protection layer is disposed corresponding to the first electronic unit and the second electronic unit, and the protection layer has an opening. At least a portion of the flexible member is disposed in the opening. The protection layer has a first Young's modulus, the flexible member has a second Young's modulus, and the first Young's modulus is greater than the second Young's modulus.

公开(公告)号：US20230207543A1

公开(公告)日：2023-06-29

申请号：US17868216

申请日：2022-07-19

申请人： Samsung Display Co., LTD.

发明人： Jae Hoon KIM

IPC分类号： H01L25/16 ,  H01L33/62 ,  H01L27/12 ,  H01L23/00

CPC分类号： H01L25/167 ,  H01L33/62 ,  H01L27/124 ,  H01L27/1248 ,  H01L24/24 ,  H01L24/25 ,  H01L2224/24051 ,  H01L2224/25175 ,  H01L2924/12041 ,  H01L2224/24147

摘要： A display device includes a plurality of bank patterns disposed on a substrate and spaced apart from each other, a plurality of electrodes disposed on the substrate and extended parallel to each other and spaced apart from each other, an insulating layer disposed on the plurality of electrodes and the plurality of bank patterns, and a plurality of light emitting elements disposed on the insulating layer, having both ends disposed on the plurality of electrodes, wherein the plurality of bank patterns include sides facing each other, and portions of the plurality of light emitting elements are disposed on the sides of the plurality of bank patterns.

公开(公告)号：US20180331057A1

公开(公告)日：2018-11-15

申请号：US15590547

申请日：2017-05-09

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： David W. Abraham ,  John M. Cotte

IPC分类号： H01L23/00 ,  H01L23/522

CPC分类号： H01L24/11 ,  H01L21/76898 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L27/18 ,  H01L39/00 ,  H01L2224/0345 ,  H01L2224/0347 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/11005 ,  H01L2224/1131 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/25175 ,  H01L2224/275 ,  H01L2224/29023 ,  H01L2224/29124 ,  H01L2224/32145 ,  H01L2224/32221 ,  H01L2224/73209 ,  H01L2224/73217 ,  H01L2224/73253 ,  H01L2224/82031 ,  H01L2224/82101 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/8382 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/11

摘要： A semiconductor structure and methods of forming the semiconductor structure include a solder bump self-aligned to a through-substrate-via, wherein the solder bump and the through-substrate-via are formed of a conductive metal material, and wherein the through-substrate-via is coupled to a buried metallization layer, which is formed of a different conductive metal material.

公开(公告)号：US20180254258A1

公开(公告)日：2018-09-06

申请号：US15759735

申请日：2016-09-14

申请人： 3DIS Technologies

发明人： Ayad Ghannam

IPC分类号： H01L23/00 ,  H01L49/02

CPC分类号： H01L24/82 ,  H01L21/4857 ,  H01L23/49822 ,  H01L24/24 ,  H01L28/10 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/24265 ,  H01L2224/24991 ,  H01L2224/24998 ,  H01L2224/82051 ,  H01L2224/821 ,  H01L2224/82101 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2924/19104 ,  H05K3/4661

摘要： The invention relates to a method for integrating at least one interconnection for the manufacture of an integrated circuit, including a step of depositing at least one insulating body onto a substrate including a horizontal surface, said insulating body comprising a first wall extending from the horizontal surface of the substrate to a high point of said insulating body and a step of depositing a one-piece electrical structure which is made of an electrically conductive material and extends on the horizontal surface of the substrate and the first wall of the insulating body, the first wall being vertically angled by more than 10 μm and having a rising slope extending from the horizontal surface of the substrate to the high point of said insulating body.

公开(公告)号：US09935028B2

公开(公告)日：2018-04-03

申请号：US14142823

申请日：2013-12-28

申请人： Global Circuit Innovations Incorporated

发明人： Erick Merle Spory

IPC分类号： H01L21/00 ,  H01L23/20 ,  H01L23/00 ,  H01L23/26 ,  H01L21/50 ,  H01L21/48 ,  H01L23/04 ,  H01L23/495 ,  H01L23/498 ,  H01L23/10

CPC分类号： H01L23/20 ,  H01L21/4803 ,  H01L21/4817 ,  H01L21/50 ,  H01L23/04 ,  H01L23/10 ,  H01L23/26 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49541 ,  H01L23/49861 ,  H01L23/564 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24175 ,  H01L2224/245 ,  H01L2224/25171 ,  H01L2224/2731 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/82102 ,  H01L2224/82103 ,  H01L2224/82214 ,  H01L2224/82815 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2924/00015 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3656 ,  H01L2924/3861 ,  H01L2224/48 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/00

摘要： A method for assembling a packaged integrated circuit is provided. The method includes placing a die into a cavity of a package base, securing the die to the package base with a die attach adhesive, printing a bond connection between a die pad of the die and a lead of the package base or a downbond, and sealing a package lid to the package base.

公开(公告)号：US20180012870A1

公开(公告)日：2018-01-11

申请号：US15695945

申请日：2017-09-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Ting Tsai ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  U-Ting Chen ,  Shih Pei Chou

IPC分类号： H01L25/065 ,  H01L21/311 ,  H01L21/3105 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768

CPC分类号： H01L25/0657 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L24/91 ,  H01L25/50 ,  H01L2224/24051 ,  H01L2224/24146 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/82031 ,  H01L2224/821 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/12036 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/82 ,  H01L2224/8203

摘要： An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.

公开(公告)号：US09385074B2

公开(公告)日：2016-07-05

申请号：US13935053

申请日：2013-07-03

申请人： STATS ChipPAC, Ltd.

发明人： Rajendra D. Pendse

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56

CPC分类号： H01L23/3121 ,  H01L21/56 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/46 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/435 ,  H01L2224/45144 ,  H01L2225/1035 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.

摘要翻译： 一种半导体封装，其具有嵌入裸片和固体垂直互连（例如柱形凸块互连），用于在z轴方向（即，垂直于模具的电路侧的方向）上增加集成。 半导体封装可以包括以面朝上配置（类似于引线键合封装）或面朝下或倒装芯片配置安装的管芯。

公开(公告)号：US09373545B2

公开(公告)日：2016-06-21

申请号：US14967640

申请日：2015-12-14

申请人： International Business Machines Corporation

发明人： Akihiro Horibe ,  Hiroyuki Mori ,  Yasumitsu Orii ,  Kuniaki Sueoka ,  Kazushige Toriyama

IPC分类号： H01L21/48 ,  H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L25/00

CPC分类号： H01L21/76898 ,  H01L21/308 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05009 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/244 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/82031 ,  H01L2224/82101 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00014

摘要： A semiconductor structure including a through electrode includes a lamination body including at least three layers, including respective vertically aligned electrode parts, the electrode part on the surface of an uppermost layer and including an aperture, the electrode part of the intermediate layer having an aperture smaller than the aperture of the uppermost layer; a through-hole extending from the aperture of the electrode part on the uppermost layer to the surface of the electrode part on a lowermost layer, the through-hole having a depressed part on a side wall thereof between the electrode parts therein; an insulating layer disposed on the entire side wall in the through-hole at a part other than on surfaces of the electrode parts; and a conductive material filling the through-hole from the surface of the electrode part on the lowermost layer to the surface of the electrode part on the uppermost layer.

摘要翻译： 包括通孔的半导体结构包括包括至少三层的层叠体，包括各自垂直排列的电极部分，最上层的表面上的电极部分，并且包括孔，中间层的电极部分具有较小的孔径 比最上层的孔径; 通孔从最上层的电极部分的孔延伸到最下层的电极部分的表面，通孔在其电极部分之间的侧壁上具有凹陷部分; 绝缘层，其设置在所述通孔的除了所述电极部的表面以外的部分的整个侧壁上; 以及从最下层的电极部的表面向最上层的电极部的表面填充贯通孔的导电性材料。

公开(公告)号：US09331010B2

公开(公告)日：2016-05-03

申请号：US12996738

申请日：2009-06-03

申请人： Wolfgang Pahl ,  Karl Weidner

发明人： Wolfgang Pahl ,  Karl Weidner

IPC分类号： H01L23/495 ,  H01L23/498 ,  B81B7/00 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L23/4985 ,  B81B7/0048 ,  B81B2207/07 ,  H01L23/498 ,  H01L23/5387 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/76155 ,  H01L2224/82007 ,  H01L2224/82102 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00

摘要： A chip (2, 3) is arranged above a top side of a flexible support (1) and mechanically decoupled from the support. Electrical connections (8, 11) of the chip are embodied using a planar connection technique. The chip can be separated from the support by an air gap or a base layer (7) composed of a soft or compressible material.

摘要翻译： 芯片（2,3）布置在柔性支撑件（1）的顶侧上方并且与支撑件机械地分离。 使用平面连接技术来实现芯片的电连接（8,11）。 芯片可以通过气隙或由软或可压缩材料构成的基层（7）与支撑体分离。