公开(公告)号：US20160260681A1

公开(公告)日：2016-09-08

申请号：US15159442

申请日：2016-05-19

申请人： International Business Machines Corporation

发明人： Hirokazu Noma ,  Yasumitsu Orii ,  Kazushige Toriyama

IPC分类号： H01L23/00

CPC分类号： H01L24/81 ,  H01L21/50 ,  H01L21/563 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05647 ,  H01L2224/11849 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/81948 ,  H01L2224/83102 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/20105 ,  H01L2924/3512 ,  H01L2924/3656 ,  H01L2924/00 ,  H01L2924/01082 ,  H01L2924/00014 ,  H01L2924/01047

摘要： A method of forming a structure for an interfacial alloy layer which is able to improve the electromigration (EM) resistance of a solder joint. More specifically, in this structure, a controlled interfacial alloy layer is provided on both sides of a solder joint. In order to form this structure, aging (maintenance of high-temperature conditions) is performed until an interfacial alloy layer of Cu3Sn has a thickness of at least 1.5 μm.

摘要翻译： 形成能够提高焊点的电迁移（EM）电阻的界面合金层的结构的方法。 更具体地说，在该结构中，在焊接接头的两侧设置受控界面合金层。 为了形成该结构，进行老化（高温条件的维持），直到Cu 3 Sn的界面合金层的厚度为至少1.5μm。

公开(公告)号：US20160056129A1

公开(公告)日：2016-02-25

申请号：US14833368

申请日：2015-08-24

申请人： International Business Machines Corporation

发明人： Akihiro Horibe ,  Hiroyuki Mori ,  Yasumitsu Orii ,  Kuniaki Sueoka ,  Kazushige Toriyama

IPC分类号： H01L25/065 ,  H01L21/308 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00

CPC分类号： H01L21/76898 ,  H01L21/308 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05009 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/244 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/82031 ,  H01L2224/82101 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00014

摘要： A semiconductor structure including a through electrode includes a lamination body including at least three layers, including respective vertically aligned electrode parts, the electrode part on the surface of an uppermost layer and including an aperture, the electrode part of the intermediate layer having an aperture smaller than the aperture of the uppermost layer; a through-hole extending from the aperture of the electrode part on the uppermost layer to the surface of the electrode part on a lowermost layer, the through-hole having a depressed part on a side wall thereof between the electrode parts therein; an insulating layer disposed on the entire side wall in the through-hole at a part other than on surfaces of the electrode parts; and a conductive material filling the through-hole from the surface of the electrode part on the lowermost layer to the surface of the electrode part on the uppermost layer.

公开(公告)号：US20150249064A1

公开(公告)日：2015-09-03

申请号：US14193875

申请日：2014-02-28

申请人： International Business Machines Corporation

发明人： Akihiro Horibe ,  Yasumitsu Orii

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/538

CPC分类号： H01L23/562 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/01014 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00014

摘要： To reduce the risk of reduction in yield due to breakage of a thin wafer or a thin chip having through silicon vias (TSVs) formed therein in a chip bonding process, and to prevent warping during handling of a chip-on-wafer (CoW). Chips are bonded to a wafer having TSVs formed therein and sealed before the wafer is thinned. Subsequently, the CoW is subjected to a process of thinning the TSV wafer, a back-surface treatment, and a process of cutting the wafer into small pieces by dicing. Although thin wafers and thin chips having TSVs formed therein are difficult to handle since the chips are bonded to the wafer before thinning and the wafer is thinned and cut into small pieces while mechanical strength thereof is increased by fixing a support to the wafer, the yield of three-dimensional stacked devices can be increased.

公开(公告)号：US10115692B2

公开(公告)日：2018-10-30

申请号：US15264964

申请日：2016-09-14

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Toyohiro Aoki ,  Takashi Hisada ,  Hiroyuki Mori ,  Eiji Nakamura ,  Yasumitsu Orii

IPC分类号： H01L21/44 ,  H01L23/00

摘要： A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.

公开(公告)号：US20180076165A1

公开(公告)日：2018-03-15

申请号：US15714146

申请日：2017-09-25

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Toyohiro Aoki ,  Takashi Hisada ,  Hiroyuki Mori ,  Eiji Nakamura ,  Yasumitsu Orii

IPC分类号： H01L23/00

CPC分类号： H01L24/14 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/27 ,  H01L24/30 ,  H01L24/742 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/3001 ,  H01L2224/73104 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079

摘要： A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.

公开(公告)号：US09391034B2

公开(公告)日：2016-07-12

申请号：US13973434

申请日：2013-08-22

申请人： International Business Machines Corporation

发明人： Hirokazu Noma ,  Yasumitsu Orii ,  Kazushige Toriyama

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/50

CPC分类号： H01L24/81 ,  H01L21/50 ,  H01L21/563 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05647 ,  H01L2224/11849 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/81948 ,  H01L2224/83102 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/20105 ,  H01L2924/3512 ,  H01L2924/3656 ,  H01L2924/00 ,  H01L2924/01082 ,  H01L2924/00014 ,  H01L2924/01047

摘要： ProblemTo improve the electromigration (EM) resistance of a solder joint.SolutionThe present invention provides a unique structure for an interfacial alloy layer which is able to improve the electromigration (EM) resistance of a solder joint, and a unique method of forming this structure. More specifically, in this unique structure, a controlled interfacial alloy layer is provided on both sides of a solder joint. In order to form this structure, aging (maintenance of high-temperature conditions) is performed until an interfacial alloy layer of Cu3Sn has a thickness of at least 1.5 μm.

摘要翻译： 问题提高焊点的电迁移（EM）电阻。 解决方案本发明提供能够提高焊点的电迁移（EM）电阻的界面合金层的独特结构，以及形成该结构的独特方法。 更具体地，在这种独特的结构中，在焊接接头的两侧设置受控界面合金层。 为了形成该结构，进行老化（高温条件的维持），直到Cu 3 Sn的界面合金层的厚度为至少1.5μm。

公开(公告)号：US20160099175A1

公开(公告)日：2016-04-07

申请号：US14967640

申请日：2015-12-14

申请人： International Business Machines Corporation

发明人： Akihiro Horibe ,  Hiroyuki Mori ,  Yasumitsu Orii ,  Kuniaki Sueoka ,  Kazushige Toriyama

IPC分类号： H01L21/768 ,  H01L25/00

CPC分类号： H01L21/76898 ,  H01L21/308 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05009 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/244 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/82031 ,  H01L2224/82101 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00014

摘要： A semiconductor structure including a through electrode includes a lamination body including at least three layers, including respective vertically aligned electrode parts, the electrode part on the surface of an uppermost layer and including an aperture, the electrode part of the intermediate layer having an aperture smaller than the aperture of the uppermost layer; a through-hole extending from the aperture of the electrode part on the uppermost layer to the surface of the electrode part on a lowermost layer, the through-hole having a depressed part on a side wall thereof between the electrode parts therein; an insulating layer disposed on the entire side wall in the through-hole at a part other than on surfaces of the electrode parts; and a conductive material filling the through-hole from the surface of the electrode part on the lowermost layer to the surface of the electrode part on the uppermost layer.

摘要翻译： 包括通孔的半导体结构包括包括至少三层的层叠体，包括各自垂直排列的电极部分，最上层的表面上的电极部分，并且包括孔，中间层的电极部分具有较小的孔径 比最上层的孔径; 通孔从最上层的电极部分的孔延伸到最下层的电极部分的表面，通孔在其电极部分之间的侧壁上具有凹陷部分; 绝缘层，其设置在所述通孔的除了所述电极部的表面以外的部分的整个侧壁上; 以及从最下层的电极部的表面向最上层的电极部的表面填充贯通孔的导电性材料。

公开(公告)号：US10833035B2

公开(公告)日：2020-11-10

申请号：US16116152

申请日：2018-08-29

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Toyohiro Aoki ,  Takashi Hisada ,  Hiroyuki Mori ,  Eiji Nakamura ,  Yasumitsu Orii

IPC分类号： H01L23/00 ,  H01L21/48

摘要： A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.

公开(公告)号：US20180076164A1

公开(公告)日：2018-03-15

申请号：US15498735

申请日：2017-04-27

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Toyohiro Aoki ,  Takashi Hisada ,  Hiroyuki Mori ,  Eiji Nakamura ,  Yasumitsu Orii

IPC分类号： H01L23/00

摘要： A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.

公开(公告)号：US09466533B2

公开(公告)日：2016-10-11

申请号：US14833368

申请日：2015-08-24

申请人： International Business Machines Corporation

发明人： Akihiro Horibe ,  Hiroyuki Mori ,  Yasumitsu Orii ,  Kuniaki Sueoka ,  Kazushige Toriyama

IPC分类号： H01L21/768 ,  H01L25/065 ,  H01L23/48 ,  H01L25/00 ,  H01L23/00 ,  H01L21/308 ,  H01L21/48 ,  H01L23/522

CPC分类号： H01L21/76898 ,  H01L21/308 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05009 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/244 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/82031 ,  H01L2224/82101 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00014

摘要： A semiconductor structure including a through electrode includes a lamination body including at least three layers, including respective vertically aligned electrode parts, the electrode part on the surface of an uppermost layer and including an aperture, the electrode part of the intermediate layer having an aperture smaller than the aperture of the uppermost layer; a through-hole extending from the aperture of the electrode part on the uppermost layer to the surface of the electrode part on a lowermost layer, the through-hole having a depressed part on a side wall thereof between the electrode parts therein; an insulating layer disposed on the entire side wall in the through-hole at a part other than on surfaces of the electrode parts; and a conductive material filling the through-hole from the surface of the electrode part on the lowermost layer to the surface of the electrode part on the uppermost layer.