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公开(公告)号：US11848272B2
公开(公告)日：2023-12-19
申请号：US17445161
申请日：2021-08-16
发明人： Akihiro Horibe , Toyohiro Aoki , Takashi Hisada
IPC分类号： H01L23/538 , H01L25/065 , H01L25/00 , H01L23/00 , H01L21/56 , H01L23/13 , H01L25/18
CPC分类号： H01L23/5381 , H01L21/568 , H01L23/13 , H01L24/14 , H01L24/98 , H01L25/0655 , H01L25/50 , H01L24/73 , H01L24/92 , H01L25/18 , H01L2224/1403 , H01L2224/16145 , H01L2224/16227 , H01L2224/73204 , H01L2224/92125 , H01L2924/1515 , H01L2924/18161
摘要： A method of fabricating a bridged multi-chip assembly structure includes providing a carrier substrate. The method further includes arranging a plurality of chips on the carrier substrate in a predetermined layout. Each chip has a front surface including a set of terminals formed thereon. The method further includes depositing a molding material between the plurality of chips and on the carrier substrate. The method further includes removing the carrier substrate from the plurality of chips fixed by the molding material. The method further includes bonding a bridge chip to corresponding sets of terminals of at least two chips of the plurality of chips fixed by the molding material.
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公开(公告)号：US20230343713A1
公开(公告)日：2023-10-26
申请号：US18344418
申请日：2023-06-29
发明人： Akihiro Horibe , Toyohiro Aoki , Takashi Hisada
IPC分类号： H01L23/538 , H01L25/065 , H01L25/00 , H01L23/00 , H01L21/56 , H01L23/13
CPC分类号： H01L23/5381 , H01L25/0655 , H01L25/50 , H01L24/14 , H01L24/98 , H01L21/568 , H01L23/13 , H01L2224/92125 , H01L24/92 , H01L2224/73204 , H01L2924/1515 , H01L2924/18161 , H01L25/18
摘要： A method of fabricating a bridged multi-chip assembly structure includes providing a carrier substrate. The method further includes arranging a plurality of chips on the carrier substrate in a predetermined layout. Each chip has a front surface including a set of terminals formed thereon. The method further includes depositing a molding material between the plurality of chips and on the carrier substrate. The method further includes removing the carrier substrate from the plurality of chips fixed by the molding material. The method further includes bonding a bridge chip to corresponding sets of terminals of at least two chips of the plurality of chips fixed by the molding material.
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公开(公告)号：US11164845B2
公开(公告)日：2021-11-02
申请号：US16777416
申请日：2020-01-30
发明人： Eiji Nakamura , Toyohiro Aoki , Takashi Hisada , Risa Miyazawa
摘要： A method for fabricating a resist structure is presented. The method includes preparing a substrate on which plural conductive pads are formed; and patterning a lower resist to form plural lower cavities. The lower resist is deposited above the substrate. Each of the plural lower cavities are located above a corresponding one of the plural conductive pads. Additionally, the method includes patterning an upper resist to form plural upper cavities. The upper resist is deposited on the lower resist. Each of the plural upper cavities are located on a corresponding one of the plural lower cavities and have a diameter larger than a diameter of the corresponding one of the plural lower cavities.
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公开(公告)号：US10833035B2
公开(公告)日：2020-11-10
申请号：US16116152
申请日：2018-08-29
发明人： Toyohiro Aoki , Takashi Hisada , Hiroyuki Mori , Eiji Nakamura , Yasumitsu Orii
摘要： A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.
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公开(公告)号：US20180294213A1
公开(公告)日：2018-10-11
申请号：US15480750
申请日：2017-04-06
发明人： Toyohiro Aoki , Takashi Hisada , Akihiro Horibe , Sayuri Hada , Eiji I. Nakamura , Kuniaki Sueoka
IPC分类号： H01L23/498 , H01L23/48 , H01L21/768
CPC分类号： H01L23/49827 , H01L21/76898 , H01L23/481 , H01L2924/00014 , H01L2924/0002
摘要： A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.
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公开(公告)号：US20180269173A1
公开(公告)日：2018-09-20
申请号：US15987029
申请日：2018-05-23
发明人： Toyohiro Aoki , Takashi Hisada , Eiji I. Nakamura
IPC分类号： H01L23/00
摘要： Wafers include multiple bulk redistribution layers. A contact pad is formed on a surface of one of the bulk redistribution layers. A final redistribution layer is formed on the surface and in contact with the contact pad. Solder is formed on the contact pad. The solder includes a pedestal portion formed to a same height as the final redistribution layer and a ball portion above the pedestal portion.
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公开(公告)号：US10037958B2
公开(公告)日：2018-07-31
申请号：US15625033
申请日：2017-06-16
发明人： Toyohiro Aoki , Takashi Hisada , Eiji I. Nakamura
IPC分类号： H01L23/00
CPC分类号： H01L24/11 , H01L24/02 , H01L24/13 , H01L24/742 , H01L24/81 , H01L24/94 , H01L2224/02166 , H01L2224/02313 , H01L2224/0239 , H01L2224/024 , H01L2224/0382 , H01L2224/03826 , H01L2224/03827 , H01L2224/0401 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/11003 , H01L2224/11013 , H01L2224/1111 , H01L2224/11312 , H01L2224/1147 , H01L2224/1148 , H01L2224/11849 , H01L2224/119 , H01L2224/13014 , H01L2224/13018 , H01L2224/13024 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/81815 , H01L2924/066 , H01L2924/0695 , H01L2924/07025 , H01L2924/14 , H01L2924/00014 , H01L2924/01029 , H01L2924/01047 , H01L2924/01201
摘要： Wafers include multiple bulk redistribution layers. A terminal contact pad is on a surface of one of the bulk redistribution layers. A final redistribution layer is formed on the surface and in contact with the terminal contact pad. The final redistribution layer is formed from a material other than a material of the plurality of bulk redistribution layers. A solder ball is formed on the terminal contact pad.
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公开(公告)号：US20180076164A1
公开(公告)日：2018-03-15
申请号：US15498735
申请日：2017-04-27
发明人： Toyohiro Aoki , Takashi Hisada , Hiroyuki Mori , Eiji Nakamura , Yasumitsu Orii
IPC分类号： H01L23/00
摘要： A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.
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公开(公告)号：US09837367B1
公开(公告)日：2017-12-05
申请号：US15297269
申请日：2016-10-19
发明人： Toyohiro Aoki , Takashi Hisada , Eiji I. Nakamura
IPC分类号： H01L23/00
CPC分类号： H01L24/11 , H01L23/3171 , H01L24/02 , H01L24/13 , H01L24/742 , H01L24/81 , H01L24/94 , H01L2224/02166 , H01L2224/024 , H01L2224/0382 , H01L2224/03826 , H01L2224/03827 , H01L2224/0401 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/11003 , H01L2224/11312 , H01L2224/1147 , H01L2224/1148 , H01L2224/11849 , H01L2224/13014 , H01L2224/13018 , H01L2224/13024 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/81815 , H01L2924/14 , H01L2924/00014 , H01L2924/01029 , H01L2924/01047 , H01L2924/01201
摘要： Wafers and methods of forming solder balls include forming a final redistribution layer over terminal contact pad on a surface of a wafer. The wafer includes multiple bulk redistribution layers. A hole is etched in the final redistribution layer to expose the terminal contact pad. Solder is injected into the hole using an injection nozzle that is in direct contact with the final redistribution layer. The final redistribution layer is etched back. The injected solder is reflowed to form a solder ball.
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公开(公告)号：US11969828B2
公开(公告)日：2024-04-30
申请号：US18296462
申请日：2023-04-06
发明人： Toyohiro Aoki , Eiji Nakamura , Takashi Hisada
CPC分类号： B23K3/0638 , B23K1/08 , B23K1/20 , B23K3/08
摘要： An injection apparatus for injection material is disclosed. The injection apparatus includes a tank for storing material. The injection apparatus further includes a head body that has a surface for contacting a substrate and an opening part opened at the surface for discharging the material in fluid-communication with the tank. The injection apparatus further includes a member connected to the opening part, in which the member allows gas to flow into and flow out from the opening part.
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