公开(公告)号：US20240363462A1

公开(公告)日：2024-10-31

申请号：US18309642

申请日：2023-04-28

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Vivek Swaminathan SRIDHARAN ,  Hung-Yun LIN ,  Qiao CHEN

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L23/3114 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0233 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05093 ,  H01L2224/13026 ,  H01L2924/15311

摘要： In some examples, a package comprises a die having a device side with circuitry formed therein; a passivation layer abutting the device side; and first and second vias coupling to the device side and extending through the passivation layer. The package includes first and second metal layers coupled to the first and second vias, respectively, the first and second metal layers abutting the passivation layer. The package includes an insulation layer abutting the first and second metal layers and separating the first and second metal layers, the insulation layer having an orifice in vertical alignment with the second metal layer. The package includes a third metal layer coupled to the second metal layer through the orifice, the third metal layer vertically aligned with the first and second metal layers. The package comprises a conductive member coupled to the third metal layer. The package includes a mold compound covering package components.

公开(公告)号：US20190221534A1

公开(公告)日：2019-07-18

申请号：US16360317

申请日：2019-03-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Chan Chen ,  Yueh-Chuan Lee

IPC分类号： H01L23/00 ,  H01L27/146

CPC分类号： H01L24/08 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L2224/02331 ,  H01L2224/02381 ,  H01L2224/034 ,  H01L2224/03616 ,  H01L2224/03622 ,  H01L2224/04042 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/0508 ,  H01L2224/05083 ,  H01L2224/05088 ,  H01L2224/05089 ,  H01L2224/05091 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05554 ,  H01L2224/05562 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48464 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/013 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/00012

摘要： Some embodiments relate to a bond pad structure of an integrated circuit (IC). The bond structure includes a bond pad and an intervening metal layer positioned below the bond pad. The intervening metal layer has a first face and a second face. A first via layer is in contact with the first face of intervening metal layer. The first via layer has a first via pattern. The bond structure also includes a second via layer in contact with the second face of the intervening metal layer. The second via layer has a second via pattern that is different than first via pattern. The second via pattern includes a first group of elongated vias extending in parallel with one another in a first direction and a second group of vias in between the first group of elongated vias. The second group of vias extend in a second direction orthogonal to the first direction.

公开(公告)号：US10084076B2

公开(公告)日：2018-09-25

申请号：US15297123

申请日：2016-10-18

申请人： DELTA ELECTRONICS, INC.

发明人： Li-Fan Lin ,  Chun-Chieh Yang ,  Wen-Chia Liao ,  Ching-Chuan Shiue ,  Shih-Peng Chen

IPC分类号： H01L29/788 ,  H01L29/778 ,  H01L23/00 ,  H01L23/495 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/20 ,  H01L23/31 ,  H01L23/535 ,  H01L29/205 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L29/7787 ,  H01L23/3171 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/535 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/7786 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/0603 ,  H01L2224/45014 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/13064 ,  H01L2924/00 ,  H01L2924/206

摘要： A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, an interlayer dielectric, an inter-source layer, an inter-source plug, an inter-drain layer, an inter-drain plug, an inter-gate layer, and an inter-gate plug. The active layer is made of III-V group semiconductors. The source electrode, the drain electrode, and the gate electrode are disposed on the active layer. The gate electrode is disposed between the source electrode and the drain electrode. The interlayer dielectric covers the source electrode, the drain electrode, and the gate electrode. The inter-source layer, the inter-drain layer, and the inter-gate layer are disposed on the interlayer dielectric. The inter-source plug is electrically connected to the source electrode and the inter-source layer. The inter-drain plug is electrically connected to the drain electrode and the inter-drain layer. The inter-gate plug is electrically connected to the gate electrode and the inter-gate layer.

公开(公告)号：USRE46784E1

公开(公告)日：2018-04-10

申请号：US14743421

申请日：2015-06-18

申请人： REALTEK SEMICONDUCTOR CORPORATION

发明人： Ying-Hsi Lin

IPC分类号： H01L23/48 ,  H01L23/485 ,  H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05558 ,  H01L2224/05599 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2224/45099

摘要： The invention is to provide a structure of IC pad and its forming method. The structure is arranged in an insulation layer and is comprised of a lower electric-conduction layer, a compound layer structure and a pad layer. The lower electric-conduction layer is arranged at an appropriate position in the insulation layer and is connected to an electric potential. The compound layer structure is arranged on the insulation layer and is composed of at least one electric-conduction layer and at least one electric-conduction connecting layer, both are inter-overlapped to each other. The pad layer is arranged on the compound layer structure.

公开(公告)号：US20180096958A1

公开(公告)日：2018-04-05

申请号：US15663531

申请日：2017-07-28

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION ,  SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION

发明人： YUNLONG KONG

IPC分类号： H01L23/00 ,  H01L27/146 ,  H04N5/369

CPC分类号： H01L24/05 ,  H01L23/3171 ,  H01L24/03 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/1469 ,  H01L2224/0212 ,  H01L2224/034 ,  H01L2224/03602 ,  H01L2224/03616 ,  H01L2224/05093 ,  H01L2224/05098 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/48227 ,  H01L2224/73265 ,  H04N5/369 ,  H01L2924/00014

摘要： A method for manufacturing a bond pad structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, and a passivation layer on the first metal layer, the passivation layer having an opening extending to the first metal layer; and filling the opening of the passivation layer with a second metal layer. The bond pad structure has a significantly increased thickness compared with the thickness of the exposed portion of the first metal layer in the opening, thereby ensuring wire bonding reliability and yield.

公开(公告)号：US09768132B2

公开(公告)日：2017-09-19

申请号：US13420342

申请日：2012-03-14

申请人： Ling Mei Lin ,  Chun Li Wu ,  Yung-Fa Lee

发明人： Ling Mei Lin ,  Chun Li Wu ,  Yung-Fa Lee

IPC分类号： H01L23/00 ,  H01L23/522

CPC分类号： H01L24/03 ,  H01L23/522 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05546 ,  H01L2224/05553 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

摘要： A semiconductor structure includes a substrate, a bond pad over the substrate, and a passivation layer over the substrate and a peripheral region of the bond pad. The bond pad has a bonding region and the peripheral region surrounding the bonding region. The passivation layer has an opening defined therein, and the opening exposes the bonding region of the bond pad. A first vertical distance between an upper surface of the passivation layer and a surface of the bonding region ranges from 30% to 40% of a second vertical distance between a lower surface of the passivation layer and an upper surface of the peripheral region.

公开(公告)号：US09741659B2

公开(公告)日：2017-08-22

申请号：US14981569

申请日：2015-12-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei Chen ,  Shih-Wei Liang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/528 ,  H01L23/00 ,  H01L21/311 ,  H01L21/48 ,  H01L23/498 ,  H01L21/768 ,  H01L23/532 ,  H01L23/31

CPC分类号： H01L23/528 ,  H01L21/311 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/53228 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/0502 ,  H01L2224/05022 ,  H01L2224/05093 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/061 ,  H01L2224/06131 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2224/05947

摘要： Electrical connections for chip scale packaging are disclosed. In one embodiment, a semiconductor device includes a post-passivation layer disposed over a substrate, the substrate having a first direction of coefficient of thermal expansion mismatch. The semiconductor device includes a first opening through the post-passivation layer, the first opening comprising a plurality of elongated apertures. A longest of the plurality of elongated apertures comprises a first dimension, wherein the first dimension is aligned substantially perpendicular to the first direction of coefficient of thermal expansion mismatch.

公开(公告)号：US20170200692A1

公开(公告)日：2017-07-13

申请号：US15472912

申请日：2017-03-29

申请人： General Electric Company

发明人： Arun Virupaksha Gowda ,  Paul Alan McConnelee

IPC分类号： H01L23/00 ,  H01L23/522 ,  H01L21/78 ,  H01L25/00 ,  H01L21/768 ,  H01L21/683 ,  H01L23/528 ,  H01L25/07

CPC分类号： H01L24/46 ,  H01L21/6835 ,  H01L21/76879 ,  H01L21/78 ,  H01L23/3164 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/85 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/03466 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/24137 ,  H01L2224/29101 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/4847 ,  H01L2224/48847 ,  H01L2224/4903 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/8203 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2924/00014 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1301 ,  H01L2924/1302 ,  H01L2924/13023 ,  H01L2924/13034 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/014 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/207

摘要： A power overlay (POL) structure includes a power device having at least one upper contact pad disposed on an upper surface of the power device, and a POL interconnect layer having a dielectric layer coupled to the upper surface of the power device and a metallization layer having metal interconnects extending through vias formed through the dielectric layer and electrically coupled to the at least one upper contact pad of the power device. The POL structure also includes at least one copper wirebond directly coupled to the metallization layer.

公开(公告)号：US09666546B1

公开(公告)日：2017-05-30

申请号：US15141571

申请日：2016-04-28

申请人： Infineon Technologies AG

发明人： Manfred Schneegans ,  Bernhard Weidgans ,  Franziska Haering

IPC分类号： H01L21/4763 ,  H01L23/00 ,  H01L21/027 ,  H01L23/31 ,  H01L21/768

CPC分类号： H01L24/06 ,  H01L21/0273 ,  H01L21/76864 ,  H01L21/76865 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/03462 ,  H01L2224/05087 ,  H01L2224/05093 ,  H01L2224/05098 ,  H01L2224/05147 ,  H01L2224/0603 ,  H01L2224/065 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45176 ,  H01L2224/45181 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48484 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/1306 ,  H01L2924/35121 ,  H01L2924/00014

摘要： A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.

公开(公告)号：US20170047345A1

公开(公告)日：2017-02-16

申请号：US15335482

申请日：2016-10-27

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： JAE-EUN LEE ,  SUNGHOON KIM

IPC分类号： H01L27/115 ,  H01L23/522 ,  H01L23/535 ,  H01L23/528

CPC分类号： H01L27/11582 ,  G11C16/08 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L24/05 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L2224/0235 ,  H01L2224/02381 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/145 ,  H01L2924/1451 ,  H01L2924/14511 ,  H01L2924/00012

摘要： A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a first metal layer, a peripheral circuit configured to control the memory cell array, a second metal layer, and a pad. The first metal layer is disposed on the memory cell array and includes a plurality of cell region interconnections connected to the memory cell array. The second metal layer is disposed on the peripheral circuit and includes a plurality of peripheral region interconnections connecting the peripheral circuit and the plurality of cell region interconnections. The pad is disposed on the second metal layer and exchanges data, an address, or a command with the peripheral circuit during operation of the device. The second metal layer is lower than the first metal layer relative to a substrate of the device.

摘要翻译： 非易失性存储器件包括包括多个存储单元的存储单元阵列，第一金属层，被配置为控制存储单元阵列的外围电路，第二金属层和衬垫。 第一金属层设置在存储单元阵列上，并且包括连接到存储单元阵列的多个单元区域互连。 第二金属层设置在外围电路上，并且包括连接外围电路和多个单元区域互连的多个周边区域互连。 焊盘设置在第二金属层上，并在设备的操作期间与外围电路交换数据，地址或命令。 第二金属层相对于器件的衬底低于第一金属层。