公开(公告)号：US12040303B2

公开(公告)日：2024-07-16

申请号：US17005362

申请日：2020-08-28

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Mitsuaki Kato ,  Takahiro Omori ,  Akihiro Goryu ,  Tomoya Fumikura ,  Kenji Hirohata ,  Tetsuya Kugimiya

IPC分类号： G01R31/66 ,  G01R27/08 ,  H01L23/00

CPC分类号： H01L24/48 ,  G01R27/08 ,  G01R31/66 ,  H01L24/49 ,  H01L2224/45111 ,  H01L2224/45123 ,  H01L2224/45124 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45166 ,  H01L2224/45179 ,  H01L2224/4518 ,  H01L2224/45181 ,  H01L2224/45184 ,  H01L2224/4813 ,  H01L2224/48458 ,  H01L2224/4852 ,  H01L2224/48723 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48757 ,  H01L2224/48766 ,  H01L2224/48779 ,  H01L2224/4878 ,  H01L2224/48781 ,  H01L2224/48784 ,  H01L2224/48823 ,  H01L2224/48824 ,  H01L2224/48855 ,  H01L2224/48857 ,  H01L2224/48866 ,  H01L2224/48879 ,  H01L2224/4888 ,  H01L2224/48881 ,  H01L2224/48884 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/01014 ,  H01L2924/0106 ,  H01L2924/01087

摘要： A semiconductor device 10 includes a pair of electrodes 16 and a conductive connection member 21 electrically bonded to the pair of electrodes 16. At least a portion of a perimeter of a bonding surface 24 of at least one of the pair of electrodes 16 and the conductive connection member 21 includes an electromigration reducing area 22.

公开(公告)号：US08076587B2

公开(公告)日：2011-12-13

申请号：US12327348

申请日：2008-12-03

申请人： David J. Mitchell ,  Anand A. Kulkarni ,  Andrew J. Burns

发明人： David J. Mitchell ,  Anand A. Kulkarni ,  Andrew J. Burns

IPC分类号： H05K1/00

CPC分类号： H05K1/183 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/29294 ,  H01L2224/29344 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45144 ,  H01L2224/45164 ,  H01L2224/45166 ,  H01L2224/45181 ,  H01L2224/45184 ,  H01L2224/4554 ,  H01L2224/45669 ,  H01L2224/45684 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/13062 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/19041 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/092 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/83205

摘要： A printed circuit board (PCB 22) capable of withstanding ultra high G forces and ultra high temperature as in a gas turbine (11). The PCB includes a substrate having a plurality of cavities (30A, 36A) formed therein for receiving components of a circuit, and conductors embedded in the PCB for electrically connecting the components together to complete the circuit. Each of the cavities has a wall (36A′) upstream of the G-forces which supports the respective component in direct contact in order to prevent the development of tensile loads in a bonding layer (37A). When the component is an integrated circuit (50), titanium conductors (63) are coupled between exposed ends of the embedded conductors and contact pads on the integrated circuit. A gold paste (51) may be inserted into interstitial gaps between the integrated circuit and the upstream wall.

摘要翻译： 一种能够承受燃气轮机（11）中的超高G力和超高温的印刷电路板（PCB 22）。 PCB包括具有形成在其中的用于接收电路部件的多个空腔（30A，36A）的基板和嵌入PCB中的导体，用于将部件电连接在一起以完成电路。 每个空腔在G力的上游具有壁（36A'），其支撑直接接触的相应部件，以防止粘合层（37A）中的拉伸载荷的发展。 当组件是集成电路（50）时，钛导体（63）耦合在嵌入式导体的暴露端和集成电路上的接触焊盘之间。 金膏（51）可以插入到集成电路和上游壁之间的间隙中。

公开(公告)号：US09887170B2

公开(公告)日：2018-02-06

申请号：US15592941

申请日：2017-05-11

申请人： Infineon Technologies AG

发明人： Manfred Schneegans ,  Bernhard Weidgans ,  Franziska Haering

IPC分类号： H01L23/52 ,  H01L23/00

CPC分类号： H01L24/06 ,  H01L21/0273 ,  H01L21/76864 ,  H01L21/76865 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/03462 ,  H01L2224/05087 ,  H01L2224/05093 ,  H01L2224/05098 ,  H01L2224/05147 ,  H01L2224/0603 ,  H01L2224/065 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45176 ,  H01L2224/45181 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48484 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/1306 ,  H01L2924/35121 ,  H01L2924/00014

摘要： A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.

公开(公告)号：US3472443A

公开(公告)日：1969-10-14

申请号：US3472443D

申请日：1966-04-12

申请人： FANSTEEL INC

发明人： HOLZL ROBERT A ,  KOENIG WILLIAM D

IPC分类号： B23K20/00 ,  H01L21/00 ,  B23K1/00 ,  B23K3/00

CPC分类号： H01L24/85 ,  B23K20/005 ,  B23K2201/40 ,  H01L24/45 ,  H01L24/78 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4518 ,  H01L2224/45181 ,  H01L2224/45183 ,  H01L2224/45184 ,  H01L2224/78301 ,  H01L2224/78302 ,  H01L2224/786 ,  H01L2224/85043 ,  H01L2224/851 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  Y10T29/49162 ,  Y10T29/49169 ,  Y10T29/49194 ,  H01L2224/48 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/00015 ,  H01L2924/2075 ,  H01L2924/2076 ,  H01L2924/20754

公开(公告)号：US09666546B1

公开(公告)日：2017-05-30

申请号：US15141571

申请日：2016-04-28

申请人： Infineon Technologies AG

发明人： Manfred Schneegans ,  Bernhard Weidgans ,  Franziska Haering

IPC分类号： H01L21/4763 ,  H01L23/00 ,  H01L21/027 ,  H01L23/31 ,  H01L21/768

CPC分类号： H01L24/06 ,  H01L21/0273 ,  H01L21/76864 ,  H01L21/76865 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/03462 ,  H01L2224/05087 ,  H01L2224/05093 ,  H01L2224/05098 ,  H01L2224/05147 ,  H01L2224/0603 ,  H01L2224/065 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45176 ,  H01L2224/45181 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48484 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/1306 ,  H01L2924/35121 ,  H01L2924/00014

摘要： A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.

公开(公告)号：US09543260B2

公开(公告)日：2017-01-10

申请号：US13958276

申请日：2013-08-02

申请人： Infineon Technologies AG

发明人： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum

IPC分类号： H01L23/538 ,  H01L23/00

CPC分类号： H01L24/06 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/70 ,  H01L24/73 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05557 ,  H01L2224/05578 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/06153 ,  H01L2224/09133 ,  H01L2224/09153 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45176 ,  H01L2224/45181 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48153 ,  H01L2224/48247 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73271 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/053 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12031 ,  H01L2924/12032 ,  H01L2924/1205 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/37099 ,  H01L2224/84

摘要： In accordance with an embodiment of the present invention, a semiconductor device includes a first bond pad disposed at a first side of a substrate. The first bond pad includes a first plurality of pad segments. At least one pad segment of the first plurality of pad segments is electrically isolated from the remaining pad segments of the first plurality of pad segments.

摘要翻译： 根据本发明的实施例，半导体器件包括设置在衬底的第一侧的第一接合焊盘。 第一接合焊盘包括第一多个焊盘段。 第一多个焊盘段的至少一个焊盘段与第一多个焊盘段的其余焊盘段电隔离。

公开(公告)号：US20160254202A1

公开(公告)日：2016-09-01

申请号：US15027346

申请日：2014-09-29

申请人： MICRO SYSTEMS ENGINEERING GMBH

发明人： Michael Krenkel ,  Albert Brandl ,  Joerg Gossler

IPC分类号： H01L21/66 ,  H01L21/78 ,  H01L23/00

CPC分类号： H01L22/32 ,  H01L21/78 ,  H01L24/45 ,  H01L24/97 ,  H01L2224/45144 ,  H01L2224/45155 ,  H01L2224/45164 ,  H01L2224/45181 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method for producing an array formed from a multiplicity of electric integrated circuits, said array being intended for separation and having a conductive connection to a central contact path for bond monitoring, said method comprising the following steps: applying conductive tracks to the array, wherein the separation region is recessed from applying said tracks, and closing the conductive connection to the central contact path by applying individual conductive connection portions, which extend between two contact paths which enclose the separation region and are arranged adjacent thereto, formed from at least one material from the group comprising the elements gold, palladium, tantalum and nickel and also comprising the alloy containing predominantly at least one of the mentioned elements.

摘要翻译： 一种用于制造由多个电集成电路形成的阵列的方法，所述阵列旨在用于分离并且具有到用于键合监测的中心接触路径的导电连接，所述方法包括以下步骤：将导电轨道施加到阵列，其中 分离区域从施加所述轨道凹陷，并且通过施加各自的导电连接部分将导电连接件闭合，各个导电连接部分在两个包围分离区域并且邻近设置的接触路径之间延伸，该接触路径由至少一种材料形成 包括元素金，钯，钽和镍的组，并且还包含主要包含至少一个所述元素的合金。

公开(公告)号：US20040188833A1

公开(公告)日：2004-09-30

申请号：US10355593

申请日：2003-01-31

发明人： Shigeyoshi Yoshida ,  Hiroshi Ono ,  Koji Kamei

IPC分类号： H01L023/34

CPC分类号： H05K1/0233 ,  H01L23/4952 ,  H01L23/66 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/745 ,  H01L2223/6611 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05599 ,  H01L2224/131 ,  H01L2224/432 ,  H01L2224/43826 ,  H01L2224/43827 ,  H01L2224/451 ,  H01L2224/45117 ,  H01L2224/45118 ,  H01L2224/45123 ,  H01L2224/45124 ,  H01L2224/45138 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/4516 ,  H01L2224/45163 ,  H01L2224/45166 ,  H01L2224/45179 ,  H01L2224/45181 ,  H01L2224/45188 ,  H01L2224/4554 ,  H01L2224/456 ,  H01L2224/45617 ,  H01L2224/45618 ,  H01L2224/45623 ,  H01L2224/45624 ,  H01L2224/45655 ,  H01L2224/45657 ,  H01L2224/4566 ,  H01L2224/45663 ,  H01L2224/45666 ,  H01L2224/45679 ,  H01L2224/45681 ,  H01L2224/45686 ,  H01L2224/45693 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/745 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01038 ,  H01L2924/01039 ,  H01L2924/01041 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01105 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/3011 ,  H03H2001/0092 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/013 ,  H01L2924/01008 ,  H01L2924/01009 ,  H01L2924/049 ,  H01L2924/053 ,  H01L2224/45015 ,  H01L2924/207

摘要： In order to provide an electronic component of a high frequency current suppression type, which can completely suppress a high frequency current to prevent an electromagnetic interference from occurring even when it is used at a high frequency, and a bonding wire for the same, the semiconductor integrated circuit device (IC) (17) operates at a high speed in using at a high frequency band, and a predetermined number of terminals (19) are provided with a high frequency current suppressor (21) for attenuating a high frequency current passing through the terminals themselves. This high frequency current suppressor (21) is a thin film magnetic substance having a range from 0.3 to 20 (nullm) in thickness, and is disposed on the entire surface of each terminal (19), covering a mounting portion to be mounted on a printed wiring circuit board (23) for mounting IC (17) and an edge including a connecting portion to a conductive pattern (25) disposed on the printed wiring circuit board (23). When the top end is connected with the conductive pattern (25) by means of a solder (27) in mounting the printed wiring circuit board (23) of IC (17), the vicinity of the mounting portion has conductivity in a using frequency band, which is less than a few tens MHz.

摘要翻译： 为了提供高频电流抑制型的电子部件，能够完全抑制高频电流，即使在高频时使用也能够发生电磁干扰，也可以使用该接合线等。 集成电路器件（IC）17在高频使用时高速工作，并且预定数量的端子（19）设置有高频电流抑制器（21），用于衰减通过的高频电流 终端本身。 该高频电流抑制器（21）是厚度为0.3〜20（μm）范围的薄膜磁性物质，并且设置在各端子（19）的整个表面上，覆盖安装部 用于安装IC（17）的印刷布线电路板（23）和包括设置在印刷布线电路板（23）上的导电图案的连接部分的边缘。 当在安装IC（17）的印刷布线电路板（23）时顶端通过焊料（27）与导电图案（25）连接时，安装部分的附近具有使用频带的导电性 ，小于几十MHz。

公开(公告)号：US20150035171A1

公开(公告)日：2015-02-05

申请号：US13958276

申请日：2013-08-02

申请人： Infineon Technologies AG

发明人： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum

IPC分类号： H01L23/00

CPC分类号： H01L24/06 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/70 ,  H01L24/73 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05557 ,  H01L2224/05578 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/06153 ,  H01L2224/09133 ,  H01L2224/09153 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45176 ,  H01L2224/45181 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48153 ,  H01L2224/48247 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73271 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/053 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12031 ,  H01L2924/12032 ,  H01L2924/1205 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/37099 ,  H01L2224/84

摘要： In accordance with an embodiment of the present invention, a semiconductor device includes a first bond pad disposed at a first side of a substrate. The first bond pad includes a first plurality of pad segments. At least one pad segment of the first plurality of pad segments is electrically isolated from the remaining pad segments of the first plurality of pad segments.

摘要翻译： 根据本发明的实施例，半导体器件包括设置在衬底的第一侧的第一接合焊盘。 第一接合焊盘包括第一多个焊盘段。 第一多个焊盘段的至少一个焊盘段与第一多个焊盘段的其余焊盘段电隔离。

公开(公告)号：US20100078202A1

公开(公告)日：2010-04-01

申请号：US12327348

申请日：2008-12-03

申请人： David J. Mitchell ,  Anand A. Kulkarni ,  Andrew J. Burns

发明人： David J. Mitchell ,  Anand A. Kulkarni ,  Andrew J. Burns

IPC分类号： H05K1/00

CPC分类号： H05K1/183 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/29294 ,  H01L2224/29344 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45144 ,  H01L2224/45164 ,  H01L2224/45166 ,  H01L2224/45181 ,  H01L2224/45184 ,  H01L2224/4554 ,  H01L2224/45669 ,  H01L2224/45684 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/13062 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/19041 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/092 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/83205

摘要： A printed circuit board (PCB 22) capable of withstanding ultra high G forces and ultra high temperature as in a gas turbine (11). The PCB includes a substrate having a plurality of cavities (30A, 36A) formed therein for receiving components of a circuit, and conductors embedded in the PCB for electrically connecting the components together to complete the circuit. Each of the cavities has a wall (36A′) upstream of the G-forces which supports the respective component in direct contact in order to prevent the development of tensile loads in a bonding layer (37A). When the component is an integrated circuit (50), titanium conductors (63) are coupled between exposed ends of the embedded conductors and contact pads on the integrated circuit. A gold paste (51) may be inserted into interstitial gaps between the integrated circuit and the upstream wall.

摘要翻译： 一种能够承受燃气轮机（11）中的超高G力和超高温的印刷电路板（PCB 22）。 PCB包括具有形成在其中的用于接收电路部件的多个空腔（30A，36A）的基板和嵌入PCB中的导体，用于将部件电连接在一起以完成电路。 每个空腔在G力的上游具有壁（36A'），其支撑直接接触的相应部件，以防止粘合层（37A）中的拉伸载荷的发展。 当组件是集成电路（50）时，钛导体（63）耦合在嵌入式导体的暴露端和集成电路上的接触焊盘之间。 金膏（51）可以插入到集成电路和上游壁之间的间隙中。