公开(公告)号：US12027465B2

公开(公告)日：2024-07-02

申请号：US17952838

申请日：2022-09-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Christopher Wyland

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/522 ,  H01L23/66 ,  H01P1/04 ,  H05K1/02

CPC classification number: H01L23/5383 ,  H01L23/5226 ,  H01L23/5387 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/50 ,  H01L24/86 ,  H01L24/91 ,  H01P1/047 ,  H05K1/0243 ,  H01L24/45 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4805 ,  H01L2224/48091 ,  H01L2224/48135 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49052 ,  H01L2224/49111 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85207 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1903 ,  H01L2924/19032 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  H05K2203/049 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2224/45147 ,  H01L2924/00014 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/20755 ,  H01L2224/45015 ,  H01L2924/20754 ,  H01L2224/45015 ,  H01L2924/20753 ,  H01L2224/45015 ,  H01L2924/20752 ,  H01L2224/45015 ,  H01L2924/20751 ,  H01L2224/49111 ,  H01L2224/48472 ,  H01L2924/00 ,  H01L2224/48472 ,  H01L2224/48091 ,  H01L2924/00 ,  H01L2924/01015 ,  H01L2924/00 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/85207 ,  H01L2924/00 ,  H01L2224/49175 ,  H01L2224/48472 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/45014 ,  H01L2924/206

Abstract: A method of improving electrical interconnections between two electrical elements is made available by providing a meta-material overlay in conjunction with the electrical interconnection. The meta-material overlay is designed to make the electrical signal propagating via the electrical interconnection to act as though the permittivity and permeability of the dielectric medium within which the electrical interconnection is formed are different than the real component permittivity and permeability of the dielectric medium surrounding the electrical interconnection. In some instances the permittivity and permeability resulting from the meta-material cause the signal to propagate as if the permittivity and permeability have negative values. Accordingly the method provides for electrical interconnections possessing enhanced control and stability of impedance, reduced noise, and reduced loss. Alternative embodiments of the meta-material overlay provide, the enhancements for conventional discrete wire bonds whilst also facilitating single integrated designs compatible with tape implementation.

公开(公告)号：US20240206063A1

公开(公告)日：2024-06-20

申请号：US18199743

申请日：2023-05-19

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Seong Ho Choi ,  Seongil Jeon

IPC: H05K1/11 ,  H05K3/46

CPC classification number: H05K1/111 ,  H05K3/4644 ,  H05K2203/049

Abstract: A circuit board includes: a substrate having a first surface and a second surface opposing each other; a first connection pad protruding from the first surface in a first direction perpendicular to the first surface of the substrate and having an upper surface and a side surface intersecting each other; a first conductive layer disposed on the upper surface of the first connection pad; and a second conductive layer disposed in contact with an upper surface of the first conductive layer and the side surface of the first connection pad.

公开(公告)号：US20240015888A1

公开(公告)日：2024-01-11

申请号：US18347086

申请日：2023-07-05

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kensuke UCHIDA

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/28 ,  H01L23/495

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K3/284 ,  H01L23/49575 ,  H05K2203/0574 ,  H05K2203/049

Abstract: A wiring board includes a first interconnect structure including a first interconnect layer and a first insulating layer, and a second interconnect structure, including a second interconnect layer and a second insulating layer, and disposed on the first interconnect structure. Interconnect width and spacing of the second interconnect layer are smaller than those of the first interconnect layer. The first insulating layer covers a side surface of the first interconnect layer and exposes an upper surface of the first interconnect layer. The second insulating layer covers the upper surface of the first interconnect layer and an upper surface of the first insulating layer. The first insulating layer and the second insulating layer include a filler. An average grain diameter and a maximum grain diameter of the filler included in the second insulating layer are smaller than those of the filler included in the first insulating layer.

公开(公告)号：US20190088801A1

公开(公告)日：2019-03-21

申请号：US16086868

申请日：2017-03-23

Applicant: Heptagon Micro Optics Pte. Ltd.

Inventor： Martin Lukas Balimann ,  Matthias Gloor ,  Philippe Bouchilloux ,  Jukka Alasirniö ,  Hartmut Rudmann ,  Nicola Spring

IPC: H01L31/0203 ,  H01L31/02 ,  H01L31/024 ,  H01L31/0232 ,  H01L33/48 ,  H01L33/62 ,  H01L33/64 ,  H01L33/58 ,  H01L27/146 ,  H01L51/52 ,  H01S5/022 ,  H01S5/024

CPC classification number: H01L31/0203 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14636 ,  H01L27/14685 ,  H01L31/02005 ,  H01L31/02019 ,  H01L31/02325 ,  H01L31/02327 ,  H01L31/024 ,  H01L31/18 ,  H01L33/48 ,  H01L33/483 ,  H01L33/58 ,  H01L33/62 ,  H01L33/647 ,  H01L51/5237 ,  H01L51/5275 ,  H01L51/529 ,  H01L2933/0033 ,  H01L2933/0058 ,  H01L2933/0066 ,  H01L2933/0075 ,  H01S5/02208 ,  H01S5/02236 ,  H01S5/02288 ,  H01S5/02469 ,  H05K1/021 ,  H05K2201/10106 ,  H05K2201/10121 ,  H05K2203/049

Abstract: An optoelectronic module assembly includes an optoelectronic module. The module includes: an active optoelectronic component in or on a mounting substrate, an optical sub-assembly, and a spacer disposed between the mounting substrate and the optical sub-assembly so as to establish a particular distance between the active optoelectronic component and the optical sub-assembly. The optoelectronic module assembly also includes a recessed substrate including first and second surfaces, wherein the second surface is in a plane closer to the optical sub-assembly than is the first surface. The optoelectronic module is mounted on the first surface. The second surface is for mounting other components.

公开(公告)号：US20190029119A1

公开(公告)日：2019-01-24

申请号：US16039719

申请日：2018-07-19

Applicant: Molex, LLC

Inventor： Patrick Weber

IPC: H05K3/12 ,  H05K1/09 ,  H05K3/22

CPC classification number: H05K3/12 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K1/095 ,  H05K3/1216 ,  H05K3/1283 ,  H05K3/22 ,  H05K3/247 ,  H05K2201/0215 ,  H05K2201/0245 ,  H05K2201/0257 ,  H05K2203/049 ,  H05K2203/1131 ,  H05K2203/1327 ,  H01L2924/00014

Abstract: A method of manufacturing includes bonding a paste material to an organic substrate by a polymer thick film (PTF) process to form a PTF trace, coating a sinterable material over the PTF trace, and sintering the sinterable material to the PTF trace.

公开(公告)号：US20180220536A1

公开(公告)日：2018-08-02

申请号：US15506035

申请日：2015-09-24

Applicant: KONINKLIJKE PHILIPS N.V.

Inventor： RALF GORDON CONRADS ,  HENDRIK HUISMAN ,  CARSTEN DEPPE ,  XI GU ,  GERO HEUSLER

IPC: H05K3/36 ,  H05K1/14 ,  H05K1/11 ,  H05K3/34

CPC classification number: H05K3/366 ,  H05K1/111 ,  H05K1/117 ,  H05K1/141 ,  H05K3/3405 ,  H05K3/403 ,  H05K2201/046 ,  H05K2203/049

Abstract: The invention describes a printed circuit board with a top side and a bottom side, the printed circuit board comprising at least two electrically conductive layers (112, 114, 116, 212, 214, 312, 314, 212i, 214i, 212j, 214j) for transmitting electrical current and at least one electrically insulating layer (102, 104, 106, 108, 202, 204, 302, 304, 202i, 204i, 202j, 204j) comprising electrically insulating material, wherein the electrically conductive layers (112, 114, 116, 212, 214, 312, 314, 212i, 214i, 212j, 214j) and the electrically insulating layer (102, 104, 106, 108, 202, 204, 302, 304, 202i, 204i, 202j, 204j) are arranged in an alternating assembly such that the two electrically conductive layers (112, 114, 116, 212, 214, 312, 314, 212i, 214i, 212j, 214j) are electrically insulated with respect to each other by means of the electrically insulating layer (102, 104, 106, 108, 202, 204, 302, 304, 202i, 204i, 202j, 204j), wherein each of the electrically conductive layers (112, 114, 116, 212, 214, 312, 314, 212i, 214i, 212j, 214j) is adapted to be coupled to a bond wire (460a, 460b) independently from the other electrically conductive layer (112, 114, 116, 212, 214, 312, 314, 212i, 214i, 212j, 214j) at a side surface of the printed circuit board being inclined to the top side and the bottom side of the printed circuit board. The invention further describes a corresponding method of fabricating the printed circuit board. The invention further describes a printed circuit board arrangement comprising the printed circuit board and a corresponding method of fabricating the printed circuit board arrangement.

公开(公告)号：US10008651B2

公开(公告)日：2018-06-26

申请号：US15267146

申请日：2016-09-16

Applicant: NICHIA CORPORATION

Inventor： Masato Ono

IPC: H01L33/62 ,  H01L25/075 ,  H01L33/48 ,  H05K1/18

CPC classification number: H01L33/62 ,  H01L25/0753 ,  H01L33/486 ,  H01L2224/48465 ,  H01L2224/49113 ,  H05K1/181 ,  H05K2201/10106 ,  H05K2203/048 ,  H05K2203/049 ,  H05K2203/1173 ,  Y02P70/611

Abstract: A first conductive pattern is disposed on a substrate. A first conductive pattern includes a first element mount portion and a first wire connection portion. A second conductive pattern is disposed on the substrate to be spaced apart from the first conductive pattern. The second conductive pattern includes a second element mount portion and a groove. The second element mount portion has a first side, a second side substantially orthogonal to the first side, and a third side substantially orthogonal to the first side and substantially parallel to the second side. The groove extends substantially parallel to the first side. A rectangular first light emitting element is disposed on the first element mount portion. A rectangular second light emitting element is disposed on the second element mount portion adjacent to the first light emitting element. A wire connects the second light emitting element to the first wire connection portion.

公开(公告)号：US09980379B2

公开(公告)日：2018-05-22

申请号：US15247970

申请日：2016-08-26

Applicant: Oclaro Japan, Inc.

Inventor： Daisuke Noguchi ,  Hiroshi Yamamoto

IPC: H05K7/00 ,  H05K1/11 ,  H05K1/14 ,  H05K1/02 ,  G02B6/42

CPC classification number: H05K1/117 ,  G02B6/4279 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/141 ,  H05K2201/09381 ,  H05K2201/10121 ,  H05K2201/1034 ,  H05K2203/049

Abstract: The second wiring pattern includes extended regions from the main body side to the projecting portions as seen in a direction in which the pair of leads extend, and wiring regions continuously spreading from the extended regions in a direction away from the main body. Supposing that a length of the wiring region from an end of the projecting portion as a reference point to a farthest position in a direction away from the main body is a first width and a width of the extended region in a direction parallel to a side opposed to the main body side through the end of the projecting portion is a second width, the first width is smaller than the second width. The second insulating substrate is sandwiched between the second wiring pattern and a base, and thereby, a capacitance is formed.

公开(公告)号：US09806053B2

公开(公告)日：2017-10-31

申请号：US15185063

申请日：2016-06-17

Applicant: MEDIATEK Inc.

Inventor： Nan-Jang Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/367 ,  H01L27/32 ,  H01L23/60 ,  H01L23/31 ,  H01L21/48 ,  H01L23/498 ,  H05K3/22

CPC classification number: H01L24/49 ,  H01L21/48 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/60 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L27/32 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1432 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H05K3/222 ,  H05K2201/10287 ,  H05K2201/10977 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A semiconductor package includes a first substrate, a first conductive layer, a first surface mount device (SMD) and a first bonding wire. The first substrate has a first top surface. The first conductive layer is formed on the first top surface and has a first conductive element and a second conductive element separated from each other. The first SMD is mounted on the first top surface, overlapping with but electrically isolated from the first conductive element. The first bonding wire electrically connects the first SMD with the first conductive layer.

公开(公告)号：US09788438B2

公开(公告)日：2017-10-10

申请号：US14368210

申请日：2012-12-12

Applicant: LG INNOTEK CO., LTD.

Inventor： Seol Hee Lim ,  Yun Kyoung Jo ,  Ae Rim Kim ,  Sai Ran Eom ,  Chang Hwa Park

IPC: H01R9/00 ,  H05K3/30 ,  H05K1/11 ,  H05K3/24 ,  C25D3/12 ,  C25D3/16 ,  C25D3/48 ,  C25D3/50 ,  C25D3/56 ,  C25D3/62 ,  C25D5/12 ,  H05K1/09 ,  H05K1/18 ,  H05K3/18 ,  C23C18/16

CPC classification number: H05K3/301 ,  C23C18/1653 ,  C25D3/12 ,  C25D3/16 ,  C25D3/48 ,  C25D3/50 ,  C25D3/562 ,  C25D3/567 ,  C25D3/62 ,  C25D5/12 ,  H05K1/092 ,  H05K1/117 ,  H05K1/18 ,  H05K3/185 ,  H05K3/244 ,  H05K2201/10159 ,  H05K2201/10909 ,  H05K2203/049 ,  H05K2203/1572 ,  Y10T29/49128

Abstract: The printed circuit board for the memory card includes an insulating layer; a mounting unit formed on a first surface of the insulating layer and electrically connected to a memory device; a terminal unit formed on a second surface of the insulating layer and electrically connected to electronic apparatuses of an outside; and metal layers formed at the mounting unit and the terminal unit and made of the same material.