公开(公告)号：US20150035171A1

公开(公告)日：2015-02-05

申请号：US13958276

申请日：2013-08-02

申请人： Infineon Technologies AG

发明人： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum

IPC分类号： H01L23/00

CPC分类号： H01L24/06 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/70 ,  H01L24/73 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05557 ,  H01L2224/05578 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/06153 ,  H01L2224/09133 ,  H01L2224/09153 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45176 ,  H01L2224/45181 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48153 ,  H01L2224/48247 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73271 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/053 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12031 ,  H01L2924/12032 ,  H01L2924/1205 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/37099 ,  H01L2224/84

摘要： In accordance with an embodiment of the present invention, a semiconductor device includes a first bond pad disposed at a first side of a substrate. The first bond pad includes a first plurality of pad segments. At least one pad segment of the first plurality of pad segments is electrically isolated from the remaining pad segments of the first plurality of pad segments.

摘要翻译： 根据本发明的实施例，半导体器件包括设置在衬底的第一侧的第一接合焊盘。 第一接合焊盘包括第一多个焊盘段。 第一多个焊盘段的至少一个焊盘段与第一多个焊盘段的其余焊盘段电隔离。

公开(公告)号：US08901569B2

公开(公告)日：2014-12-02

申请号：US13578842

申请日：2011-02-18

申请人： Hosei Hirano

发明人： Hosei Hirano

IPC分类号： H01L29/15 ,  H01L23/00

CPC分类号： H01L24/48 ,  H01L24/05 ,  H01L24/33 ,  H01L24/45 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/29111 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45184 ,  H01L2224/45565 ,  H01L2224/45647 ,  H01L2224/4847 ,  H01L2224/48491 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/83205 ,  H01L2224/85205 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/20751 ,  H01L2924/351 ,  H01L2224/05556 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/45147 ,  H01L2924/00012 ,  H01L2924/2075

摘要： Provided is a power semiconductor device comprising a bonding joint that, even under a temperature environment of 150° C. or greater enabling operation of a wide bandgap semiconductor, reduces cracking-destruction occurring owing to thermal cycle while conductively connecting an electrode, connection terminal, and semiconductor device substrate.It is a power semiconductor device capable of operating under a temperature of 150° C. or greater having an electrode laminated on a wide bandgap semiconductor substrate and a connection terminal joined to the electrode for connection to external wiring, which power semiconductor device is characterized in that difference among the three coefficients of linear expansion of the electrode, a core of the connection terminal, and the semiconductor device substrate is 5.2×10−6/K at maximum, and that it comprises a joint that directly joins the connection terminal and the electrode.

摘要翻译： 提供一种功率半导体器件，其包括接合接头，即使在150℃以上的温度环境下，能够进行宽带隙半导体的操作也能够减少由于热循环而产生的破坏破坏，同时导电连接电极，连接端子， 和半导体器件衬底。 它是能够在150℃或更高的温度下操作的功率半导体器件，其具有层叠在宽带隙半导体衬底上的电极和连接到用于连接到外部布线的电极的连接端子，该功率半导体器件的特征在于 电极，连接端子的芯和半导体器件基板的三个线膨胀系数之间的差异最大为5.2×10-6 / K，并且包括直接连接连接端子和 电极。

公开(公告)号：US08394678B2

公开(公告)日：2013-03-12

申请号：US12626069

申请日：2009-11-25

申请人： Kei Murayama ,  Akinori Shiraishi ,  Mitsuhiro Aizawa

发明人： Kei Murayama ,  Akinori Shiraishi ,  Mitsuhiro Aizawa

IPC分类号： H01L21/00 ,  H01L23/02 ,  H01L23/22 ,  H01L23/24 ,  H01L23/52

CPC分类号： H01L23/49572 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/49555 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/91 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0233 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45184 ,  H01L2224/4554 ,  H01L2224/45684 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/20754 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A plurality of chip sealing bodies stacked on a wiring substrate with a connection terminal. The chip sealing body includes a semiconductor chip having a semiconductor integrated circuit, a pad and a conductive connecting material, and a resin sealing the semiconductor chip. The chip sealing body is shaped into a cubic form in which a portion of the conductive connecting material except an end portion located on an external device side and all surfaces of semiconductor chip is sealed by the resin and the end portion of the conductive connecting material located on the external device side is exposed from the cubic form. A conductive bonding wire connects the end portions of the conductive connecting materials and the connection terminal respectively. A resin sealing material seals the plurality of chip sealing bodies, the conductive bonding wire, and the wiring substrate.

摘要翻译： 堆叠在具有连接端子的布线基板上的多个芯片密封体。 芯片密封体包括具有半导体集成电路的半导体芯片，焊盘和导电连接材料以及密封半导体芯片的树脂。 芯片密封体成形为立方体，其中位于外部装置侧的端部以外的导电性连接材料的一部分和半导体芯片的所有表面被树脂密封，导电性连接材料的端部位于 在外部设备一侧暴露于立方体形式。 导电接合线分别连接导电连接材料的端部和连接端子。 树脂密封材料密封多个芯片密封体，导电接合线和布线基板。

公开(公告)号：US20120325517A1

公开(公告)日：2012-12-27

申请号：US13168675

申请日：2011-06-24

申请人： Cyprian Uzoh ,  Craig Mitchell

发明人： Cyprian Uzoh ,  Craig Mitchell

IPC分类号： H01B5/00 ,  H01B13/00

CPC分类号： H01B13/0036 ,  H01L24/43 ,  H01L24/45 ,  H01L2224/43 ,  H01L2224/43848 ,  H01L2224/45015 ,  H01L2224/45105 ,  H01L2224/45109 ,  H01L2224/45111 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/4516 ,  H01L2224/45163 ,  H01L2224/4518 ,  H01L2224/45184 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45573 ,  H01L2224/45605 ,  H01L2224/45609 ,  H01L2224/45611 ,  H01L2224/45644 ,  H01L2224/45647 ,  H01L2224/45655 ,  H01L2224/45657 ,  H01L2224/4568 ,  H01L2224/45686 ,  H01L2224/45693 ,  H01L2224/45887 ,  H01L2224/45893 ,  H01L2224/48 ,  H01L2224/85207 ,  H01L2924/01015 ,  H01L2924/10253 ,  Y10T29/49117 ,  H01L2924/01074 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/01005 ,  H01L2924/01006

摘要： A wire structure, which may be configured for a semiconductor device, is disclosed. The wire may include an elongate flexible core formed of a conductor material and a cladding layer covering an outer surface of the core. The cladding layer may be a conductor. In various aspects the cladding layer and core have a different grain sizes. An average grain size of the core material may several orders of magnitude greater than an average grain size of the cladding layer material. The cladding layer may be an alloy having a varying concentration of a minor component across its thickness. Methods of forming a wire structure are also disclosed.

摘要翻译： 公开了一种可被配置用于半导体器件的导线结构。 线可以包括由导体材料形成的细长柔性芯和覆盖芯的外表面的覆层。 包层可以是导体。 在各个方面，包覆层和芯具有不同的晶粒尺寸。 芯材的平均晶粒尺寸可以比包覆层材料的平均晶粒尺寸大几个数量级。 包覆层可以是在其厚度上具有不同浓度的次要组分的合金。 还公开了形成线结构的方法。

公开(公告)号：US08018065B2

公开(公告)日：2011-09-13

申请号：US12039335

申请日：2008-02-28

申请人： Ken Lam

发明人： Ken Lam

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/12 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45138 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45166 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48465 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/78 ,  H01L2924/00

摘要： A wafer-level, batch processed, die-sized integrated circuit (IC) package with both top and bottom side electrical connections is disclosed. In one aspect, a number of bonding wires can be attached to bond pads on the top side (active circuit side) of an IC wafer. Trenches can be formed in the wafer at scribe regions and the bonding wires can extend through the trench. The trench can be filled with coating material. The bonding wires can be partially exposed on the top and/or bottom sides of the wafer to distribute electrical connections from the bond pads to the top and/or bottom sides of the wafer.

摘要翻译： 公开了具有顶侧和底侧电连接的晶片级批量处理的模具尺寸集成电路（IC）封装。 一方面，多个接合线可以附接到IC晶片的顶侧（有源电路侧）上的接合焊盘。 可以在划线区域的晶片中形成沟槽，并且接合线可以延伸穿过沟槽。 沟槽可以填充涂层材料。 接合线可以部分地暴露在晶片的顶部和/或底部，以将电连接从接合焊盘分配到晶片的顶部和/或底部。

公开(公告)号：US07923851B2

公开(公告)日：2011-04-12

申请号：US12722784

申请日：2010-03-12

申请人： Belgacem Haba ,  Brian Marcucci

发明人： Belgacem Haba ,  Brian Marcucci

IPC分类号： H01L23/48

CPC分类号： H01L23/552 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/66 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2223/6611 ,  H01L2223/6622 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4556 ,  H01L2224/45565 ,  H01L2224/45599 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48464 ,  H01L2224/48471 ,  H01L2224/48505 ,  H01L2224/48599 ,  H01L2224/48799 ,  H01L2224/49052 ,  H01L2224/49095 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2224/85045 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/20752 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/4569 ,  H01L2224/05644 ,  H01L2224/45184 ,  H01L2224/05647 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A microelectronic assembly can include a microelectronic device having device contacts exposed at a surface thereof and an interconnection element having element contacts and having a face adjacent to the microelectronic device. Conductive elements, e.g., wirebonds connect the device contacts with the element contacts and have portions extending in runs above the surface of the microelectronic device. A conductive layer has a conductive surface disposed at at least a substantially uniform distance above or below the plurality of the runs of the conductive elements. In some cases, the conductive material can have first and second dimensions in first and second horizontal directions which are smaller than first and second corresponding dimensions of the microelectronic device. The conductive material is connectable to a source of reference potential so as to achieve a desired impedance for the conductive elements.

摘要翻译： 微电子组件可以包括具有在其表面处暴露的器件触点的微电子器件和具有元件触点并具有与微电子器件相邻的面的互连元件。 导电元件例如引线将器件触点与元件触点连接，并具有在微电子器件的表面上方延伸的部分。 导电层具有导电表面，该导电表面设置成在多个导电元件的行程之上或之下至少基本均匀的距离。 在一些情况下，导电材料可以在第一和第二水平方向上具有小于微电子器件的第一和第二对应尺寸的第一和第二尺寸。 导电材料可连接到参考电位源，以便实现导电元件所需的阻抗。

公开(公告)号：US20100078202A1

公开(公告)日：2010-04-01

申请号：US12327348

申请日：2008-12-03

申请人： David J. Mitchell ,  Anand A. Kulkarni ,  Andrew J. Burns

发明人： David J. Mitchell ,  Anand A. Kulkarni ,  Andrew J. Burns

IPC分类号： H05K1/00

CPC分类号： H05K1/183 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/29294 ,  H01L2224/29344 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45144 ,  H01L2224/45164 ,  H01L2224/45166 ,  H01L2224/45181 ,  H01L2224/45184 ,  H01L2224/4554 ,  H01L2224/45669 ,  H01L2224/45684 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/13062 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/19041 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/092 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/83205

摘要： A printed circuit board (PCB 22) capable of withstanding ultra high G forces and ultra high temperature as in a gas turbine (11). The PCB includes a substrate having a plurality of cavities (30A, 36A) formed therein for receiving components of a circuit, and conductors embedded in the PCB for electrically connecting the components together to complete the circuit. Each of the cavities has a wall (36A′) upstream of the G-forces which supports the respective component in direct contact in order to prevent the development of tensile loads in a bonding layer (37A). When the component is an integrated circuit (50), titanium conductors (63) are coupled between exposed ends of the embedded conductors and contact pads on the integrated circuit. A gold paste (51) may be inserted into interstitial gaps between the integrated circuit and the upstream wall.

摘要翻译： 一种能够承受燃气轮机（11）中的超高G力和超高温的印刷电路板（PCB 22）。 PCB包括具有形成在其中的用于接收电路部件的多个空腔（30A，36A）的基板和嵌入PCB中的导体，用于将部件电连接在一起以完成电路。 每个空腔在G力的上游具有壁（36A'），其支撑直接接触的相应部件，以防止粘合层（37A）中的拉伸载荷的发展。 当组件是集成电路（50）时，钛导体（63）耦合在嵌入式导体的暴露端和集成电路上的接触焊盘之间。 金膏（51）可以插入到集成电路和上游壁之间的间隙中。

公开(公告)号：US20060141814A1

公开(公告)日：2006-06-29

申请号：US11355451

申请日：2006-02-16

申请人： Che-Yu Li

发明人： Che-Yu Li

IPC分类号： H01R12/00

CPC分类号： H01L23/49827 ,  G01R1/0466 ,  G01R1/06755 ,  H01L21/486 ,  H01L23/49811 ,  H01L24/45 ,  H01L24/49 ,  H01L24/72 ,  H01L2224/451 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/45173 ,  H01L2224/45184 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01R4/58 ,  H01R12/52 ,  H01R12/714 ,  H01R12/716 ,  H01R13/24 ,  H01R13/2407 ,  H01R13/33 ,  H05K3/325 ,  H01L2924/00 ,  H01L2224/05599

摘要： An electrical contact (2) and method of making the electrical contact (2), and a connector (11) and method making the connector (11), wherein the electrical contact (2) is an electrically conducting, interlaced mesh (40), with edges of the mesh providing multiple contact points for edgewise electrical connection of the electrical contact (2), wherein the mesh (40) is annealed while restrained in the form of the electrical contact (2) wherein the mesh (40) is free of internal elastic strain, or the mesh (40) is hardened, and wherein the connector (11) retains the electrical contact (2) for edgewise connection.

公开(公告)号：US20180182690A1

公开(公告)日：2018-06-28

申请号：US15851007

申请日：2017-12-21

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Li Zhong JIN ,  Li Hui LU ,  Chun Chao FEI ,  Po Yuan CHIANG ,  Ya Ping WANG

IPC分类号： H01L23/49 ,  H01L23/485 ,  H01L23/00 ,  H01L21/02

CPC分类号： H01L23/49 ,  H01L21/02123 ,  H01L23/485 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/05098 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45184 ,  H01L2224/48463 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01008

摘要： A packaging structure and a method for fabricating the packaging structure are provided. The packaging structure includes a base substrate including a solder pad body region and a trench region adjacent to and around the solder pad body region. The packaging structure also includes a passivation layer on a surface of the base substrate and exposing the solder pad body region and the trench region. In addition, the packaging structure includes a main body solder pad on the solder pad body region of the base substrate, and one or more trenches on the trench region of the base substrate and between the passivation layer and the main body solder pad. Further, the packaging structure includes a bonding conductive wire having one end connected to the main body solder pad.

公开(公告)号：US09887170B2

公开(公告)日：2018-02-06

申请号：US15592941

申请日：2017-05-11

申请人： Infineon Technologies AG

发明人： Manfred Schneegans ,  Bernhard Weidgans ,  Franziska Haering

IPC分类号： H01L23/52 ,  H01L23/00

CPC分类号： H01L24/06 ,  H01L21/0273 ,  H01L21/76864 ,  H01L21/76865 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/03462 ,  H01L2224/05087 ,  H01L2224/05093 ,  H01L2224/05098 ,  H01L2224/05147 ,  H01L2224/0603 ,  H01L2224/065 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45176 ,  H01L2224/45181 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48484 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/1306 ,  H01L2924/35121 ,  H01L2924/00014

摘要： A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.