公开(公告)号：US11929405B2

公开(公告)日：2024-03-12

申请号：US17228973

申请日：2021-04-13

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  John Twynam

IPC: H01L29/40 ,  H01L21/765 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/402 ,  H01L21/765 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: In an embodiment, a Group III nitride-based transistor device includes a source electrode, a drain electrode and a gate electrode positioned on a first major surface of a Group III nitride based-based layer, wherein the gate electrode is laterally arranged between the source electrode and the drain electrode, a passivation layer arranged on the first major surface and a field plate coupled to the source electrode, the field plate having a lower surface arranged on the passivation layer. The field plate is laterally arranged between and laterally spaced apart from the gate electrode and the drain electrode.

公开(公告)号：US11869963B2

公开(公告)日：2024-01-09

申请号：US17733009

申请日：2022-04-29

Applicant: Infineon Technologies AG

Inventor： John Twynam ,  Albert Birner ,  Helmut Brech

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/265 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207 ,  H01L29/32 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/0254 ,  H01L21/26546 ,  H01L29/04 ,  H01L29/0684 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/32 ,  H01L29/66462

Abstract: A semiconductor device includes a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposing the first surface, at least one mesa positioned on the first surface, each mesa including an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface and a parasitic channel suppression region positioned laterally adjacent the boundary.

公开(公告)号：US20210336043A1

公开(公告)日：2021-10-28

申请号：US17237178

申请日：2021-04-22

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  John Twynam

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66

Abstract: In an embodiment, a Group III nitride-based transistor device includes a first passivation layer arranged on a first major surface of a Group III nitride-based layer, a second passivation layer arranged on the first passivation layer, a source ohmic contact, a drain ohmic contact and a gate positioned on the first major surface of a Group III nitride-based layer, and a field plate, the field plate being laterally arranged between and spaced apart from the gate and the drain ohmic contact.

公开(公告)号：US10707818B1

公开(公告)日：2020-07-07

申请号：US16219025

申请日：2018-12-13

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Richard Wilson

IPC: H03F3/187 ,  H03F3/195 ,  H03F1/56 ,  H03F3/193 ,  H03H7/38 ,  H03F3/213

Abstract: A packaged amplifier circuit includes an RF package with a die pad, and RF input and output leads extending away from the die pad opposite directions. An RF transistor die is mounted on the die pad such that a first outer edge side of the RF transistor die faces the first RF lead and a second outer edge side of the RF transistor die faces the second RF lead. A passive electrical connector is integrally formed in the RF transistor die. The passive electrical connector includes a first end connection point closer to the first outer edge side, and a second end connection point closer to the second outer edge side. A first discrete reactive device is mounted on the die pad between the first outer edge side and the first RF lead. The passive electrical connector electrically couples the first discrete reactive device to the second RF lead.

公开(公告)号：US10340334B2

公开(公告)日：2019-07-02

申请号：US15986942

申请日：2018-05-23

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum ,  Michaela Braun ,  Christian Eckl

IPC: H01L29/06 ,  H01L21/265 ,  H01L21/768 ,  H01L23/528 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H03F1/02 ,  H03F3/193 ,  H01L23/48

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity ρ≥100 Ohm.cm, a front surface and a rear surface. An LDMOS transistor is arranged in the semiconductor substrate. A RESURF structure including a doped buried layer is arranged in the semiconductor substrate. The LDMOS transistor includes a body contact region doped with a first conductivity type, and a source region disposed in the body contact region and doped with a second conductivity type opposite the first conductivity type. The source region includes a first well and a second well of the same second conductivity type. The first well is more highly doped than the second well. The first well extends from inside the body contact region to outside of a lateral extent of the body contact region in a direction towards a source side of a gate of the LDMOS transistor.

公开(公告)号：US20180350981A1

公开(公告)日：2018-12-06

申请号：US16100676

申请日：2018-08-10

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum ,  Michaela Braun ,  Jan Ropohl

IPC: H01L29/78 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L29/10 ,  H01L29/66 ,  H01L23/528

CPC classification number: H01L29/7816 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L29/1095 ,  H01L29/66681

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a LDMOS transistor in the front surface, and a metallization structure arranged on the front surface. The metallization structure includes at least one cavity arranged in at least one dielectric layer. Related methods of manufacture are also described.

公开(公告)号：US20180082853A1

公开(公告)日：2018-03-22

申请号：US15273303

申请日：2016-09-22

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech

IPC: H01L21/3105 ,  H01L29/205 ,  H01L29/20 ,  H01L21/02

CPC classification number: H01L21/31056 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/31053 ,  H01L21/76229 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/7786

Abstract: In an embodiment, a method of planarising a surface includes applying a first layer to a surface including a protruding region including at least one compound semiconductor and a stop layer on an upper surface such that the first layer covers the surface and the protruding region, removing a portion of the first layer above the protruding region and forming an indentation in the first layer above the protruding region, the protruding region remaining covered by material of the first layer, and progressively removing an outermost surface of the first layer to produce a planarised surface including the stop layer on the upper surface of the protruding region and an outer surface of the first layer.

公开(公告)号：US20170372986A1

公开(公告)日：2017-12-28

申请号：US15192283

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/288 ,  H01L21/768 ,  H01L29/78 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L21/2885 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76841 ,  H01L21/76846 ,  H01L21/76898 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/404 ,  H01L29/4175 ,  H01L29/7816 ,  H01L29/7835

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate, a LDMOS transistor arranged in a front surface of the semiconductor substrate and a conductive through substrate via. The conductive through substrate via includes a via extending from the front surface to a rear surface of the semiconductor substrate, a conductive plug filling a first portion of the via and a conductive liner layer lining side walls of a second portion of the via and electrically coupled to the conductive plug.

公开(公告)号：US20140239411A1

公开(公告)日：2014-08-28

申请号：US13776153

申请日：2013-02-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Helmut Brech ,  Albert Birner

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/76898 ,  H01L21/823431 ,  H01L23/481 ,  H01L27/1211 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/73 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In accordance with an embodiment of the present invention, a semiconductor chip includes a device region disposed in or over a substrate, a doped region disposed in the device region, and a through via disposed in the substrate. The through via extends through the doped region.

Abstract translation: 根据本发明的实施例，半导体芯片包括设置在衬底中或衬底上的器件区域，设置在器件区域中的掺杂区域和设置在衬底中的通孔。 通孔延伸穿过掺杂区域。

公开(公告)号：US20240413212A1

公开(公告)日：2024-12-12

申请号：US18808702

申请日：2024-08-19

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Jphn Twynam

IPC: H01L29/40 ,  H01L21/765 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

Abstract: In an embodiment, a Group III nitride-based transistor device includes a first passivation layer arranged on a first major surface of a Group III nitride-based layer, a second passivation layer arranged on the first passivation layer, a source ohmic contact, a drain ohmic contact and a gate positioned on the first major surface of a Group III nitride-based layer, and a field plate, the field plate being laterally arranged between and spaced apart from the gate and the drain ohmic contact.