公开(公告)号：US20240234231A1

公开(公告)日：2024-07-11

申请号：US18617517

申请日：2024-03-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christopher Daniel MANACK ,  Patrick Francis THOMPSON ,  Qiao CHEN

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/315 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/48465 ,  H01L2224/73207 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/07025 ,  H01L2924/19104

Abstract: In examples, a semiconductor device comprises a semiconductor package including a mold compound covering a semiconductor die. The semiconductor package has a surface and a cavity formed in the surface. The semiconductor device comprises an electronic device positioned within the cavity, the electronic device coupled to the semiconductor die via a conductive terminal extending through the mold compound.

公开(公告)号：US20230065075A1

公开(公告)日：2023-03-02

申请号：US17463047

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Qiao CHEN ,  Vivek Swaminathan SRIDHARAN ,  Christopher Daniel MANACK ,  Patrick Francis THOMPSON ,  Jonathan Andrew MONTOYA ,  Salvatore Frank PAVONE

IPC: H01L23/00

Abstract: In some examples a wafer chip scale package (WCSP) includes a semiconductor die having a device side in which a circuit is formed, and a redistribution layer (RDL) coupled to the device side that is positioned within an insulating member. In addition, the WCSP includes a scribe seal circumscribing the circuit along the device side, wherein the RDL abuts the scribe seal. Further, the WCSP includes a conductive member coupled to the RDL. The conductive member is configured to receive a solder member, and the insulating member does not extend along the device side of the semiconductor die between the conductive member and a portion of an outer perimeter of the WCSP closest to the conductive member.

公开(公告)号：US20220059423A1

公开(公告)日：2022-02-24

申请号：US17001429

申请日：2020-08-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christopher Daniel MANACK ,  Patrick Francis THOMPSON ,  Qiao CHEN

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: In examples, a semiconductor device comprises a semiconductor package including a mold compound covering a semiconductor die. The semiconductor package has a surface and a cavity formed in the surface. The semiconductor device comprises an electronic device positioned within the cavity, the electronic device coupled to the semiconductor die via a conductive terminal extending through the mold compound.

公开(公告)号：US20240363462A1

公开(公告)日：2024-10-31

申请号：US18309642

申请日：2023-04-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek Swaminathan SRIDHARAN ,  Hung-Yun LIN ,  Qiao CHEN

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/3114 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0233 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05093 ,  H01L2224/13026 ,  H01L2924/15311

Abstract: In some examples, a package comprises a die having a device side with circuitry formed therein; a passivation layer abutting the device side; and first and second vias coupling to the device side and extending through the passivation layer. The package includes first and second metal layers coupled to the first and second vias, respectively, the first and second metal layers abutting the passivation layer. The package includes an insulation layer abutting the first and second metal layers and separating the first and second metal layers, the insulation layer having an orifice in vertical alignment with the second metal layer. The package includes a third metal layer coupled to the second metal layer through the orifice, the third metal layer vertically aligned with the first and second metal layers. The package comprises a conductive member coupled to the third metal layer. The package includes a mold compound covering package components.