公开(公告)号：US09941236B2

公开(公告)日：2018-04-10

申请号：US15245298

申请日：2016-08-24

Applicant: Renesas Electronics Corporation

Inventor： Tadahiro Miwatashi

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L24/45 ,  H01L21/76816 ,  H01L22/32 ,  H01L23/4952 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45644 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/00

Abstract: To prevent cracks of an interlayer insulation film at the time of wire bonding while maintaining adhesion of an aluminum pad electrode and the interlayer insulation film in a semiconductor device in which the aluminum pad electrode and a lead frame are connected with bonding wire by a ball bonding technology. In a bonding pad that is configured to have multiple pad electrodes each with two or more layers, the pad electrodes being electrically connected with one another through vias, the vias are not arranged under an area to which a capillary end of a wire bonder contacts at the time of the wire bonding.

公开(公告)号：US20170110429A1

公开(公告)日：2017-04-20

申请号：US14886521

申请日：2015-10-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： CHIH-KAI CHENG ,  CHENG-CHIEH HSIEH ,  SHIH-WEN HUANG

IPC: H01L23/00 ,  H01L21/768

CPC classification number: H01L24/32 ,  H01L21/76816 ,  H01L21/7685 ,  H01L21/76898 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/02166 ,  H01L2224/0221 ,  H01L2224/0361 ,  H01L2224/0391 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/08054 ,  H01L2224/08059 ,  H01L2224/32113 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device with an anti-pad peeling structure is disclosed. The semiconductor device includes: a semiconductor substrate including a Through Substrate Via (TSV); a dielectric layer on the semiconductor substrate and including a plurality of recesses therein; and a pad above the semiconductor substrate to cover a portion of the dielectric layer and extend to the recesses; wherein the pad extends to the plurality of recesses, and a plurality of contact points are confined in the recesses between the pad and the conductive layer, and each of the contact points is at least partially excluded from a boundary of the TSV when being seen from a top-down perspective.

公开(公告)号：US20170062313A1

公开(公告)日：2017-03-02

申请号：US15245298

申请日：2016-08-24

Applicant: Renesas Electronics Corporation

Inventor： Tadahiro MIWATASHI

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L24/45 ,  H01L21/76816 ,  H01L22/32 ,  H01L23/4952 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45644 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/00

Abstract: To prevent cracks of an interlayer insulation film at the time of wire bonding while maintaining adhesion of an aluminum pad electrode and the interlayer insulation film in a semiconductor device in which the aluminum pad electrode and a lead frame are connected with bonding wire by a ball bonding technology. In a bonding pad that is configured to have multiple pad electrodes each with two or more layers, the pad electrodes being electrically connected with one another through vias, the vias are not arranged under an area to which a capillary end of a wire bonder contacts at the time of the wire boding.

Abstract translation: 为了防止引线接合时的层间绝缘膜的裂纹，同时保持铝焊盘电极和引线框通过接合线与接合线连接的半导体器件中的铝焊盘电极和层间绝缘膜的粘合 技术。 在被配置为具有各自具有两层或更多层的多个焊盘电极的接合焊盘中，焊盘电极通过通孔彼此电连接，通孔不布置在引线接合器的毛细管端部接触的区域 电线编织的时间。

公开(公告)号：US09536847B2

公开(公告)日：2017-01-03

申请号：US14884438

申请日：2015-10-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiu-Ping Wei ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Ying-Ju Chen ,  Yu-Wen Liu

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L21/768 ,  H01L21/76877 ,  H01L23/48 ,  H01L23/481 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/0509 ,  H01L2224/05092 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012

Abstract: An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.

Abstract translation: 一个实施例是一种凸块接合焊盘结构，其包括基板，该基板包括顶层，设置在顶层上的加强垫，顶层上的中间层，设置在中间层上的中间连接垫，中间层上方的外层 层和通过外层中的开口连接到中间连接焊盘的凸块下金属（UBM）。 另外的实施例可以包括将中间连接垫机械连接到加强垫的通孔。 通孔可以包括选自由固体通孔，基本上环形的通孔或五个五孔的通孔组成的组的特征。 然而，另一实施例可以包括辅助加强垫，以及将加强垫机械连接到辅助加强垫的第二通孔。

公开(公告)号：US20160104666A1

公开(公告)日：2016-04-14

申请号：US14512562

申请日：2014-10-13

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee

IPC: H01L23/498 ,  H01L21/683 ,  H01L21/78 ,  H01L25/07 ,  H01L21/48

CPC classification number: H01L24/46 ,  H01L21/6835 ,  H01L21/76879 ,  H01L21/78 ,  H01L23/3164 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/85 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/03466 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/24137 ,  H01L2224/29101 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/4847 ,  H01L2224/48847 ,  H01L2224/4903 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/8203 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2924/00014 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1301 ,  H01L2924/1302 ,  H01L2924/13023 ,  H01L2924/13034 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/014 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/207

Abstract: A power overlay (POL) structure includes a power device having at least one upper contact pad disposed on an upper surface of the power device, and a POL interconnect layer having a dielectric layer coupled to the upper surface of the power device and a metallization layer having metal interconnects extending through vias formed through the dielectric layer and electrically coupled to the at least one upper contact pad of the power device. The POL structure also includes at least one copper wirebond directly coupled to the metallization layer.

Abstract translation: 功率覆盖（POL）结构包括具有设置在功率器件的上表面上的至少一个上接触焊盘的功率器件，以及具有耦合到功率器件的上表面的电介质层的POL互连层和金属化层 具有延伸穿过通过介电层形成的通孔并且电耦合到功率器件的至少一个上接触焊盘的金属互连。 POL结构还包括直接耦合到金属化层的至少一个铜引线键。

公开(公告)号：US20150353343A1

公开(公告)日：2015-12-10

申请号：US14732998

申请日：2015-06-08

Applicant: Robert Bosch GmbH

Inventor： Daniel Christoph MEISEL ,  Christoph SCHELLING ,  Torsten KRAMER ,  Jens FREY

IPC: B81B7/00

CPC classification number: B81B7/007 ,  B81B2207/012 ,  B81B2207/07 ,  B81C1/00095 ,  B81C1/00238 ,  B81C2203/0792 ,  H01L23/481 ,  H01L23/522 ,  H01L24/05 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05094 ,  H01L2224/05096 ,  H01L2224/05097 ,  H01L2224/05098 ,  H01L2224/131 ,  H01L2924/1461 ,  H01L2924/01029 ,  H01L2924/014

Abstract: Measures are provided which are used for stabilizing the substructure of the connecting areas of ASIC elements. These measures relate to ASIC elements including an ASIC substrate, into which electrical circuit functions are integrated, and including an ASIC layer structure on the ASIC substrate, which includes multiple wiring levels for the circuit functions, which are separated from one another by insulation layers and are interconnected via metallic plugs. At least one connecting area for placing wire bonds or for wafer bonding is implemented in at least one of the uppermost wiring levels. At least one chain of metallic plugs arranged vertically in a direct line is implemented in the ASIC layer structure below the connecting area, which extends from the uppermost wiring level up to the ASIC substrate or oxide trenches introduced therein.

Abstract translation: 提供了用于稳定ASIC元件的连接区域的子结构的措施。 这些措施涉及ASIC元件，包括集成了电路功能的ASIC基板，并且在ASIC基板上包括ASIC层结构，其包括用于电路功能的多个布线层，它们通过绝缘层彼此分开，并且 通过金属插头互连。 用于放置线接合或用于晶片接合的至少一个连接区域在至少一个最上面的布线层中实现。 在直接布线垂直布置的至少一个金属插塞链在从连接区域下方的ASIC层结构中实现，该连接区域从最上面的布线层向上延伸到ASIC衬底或引入其中的氧化物沟槽。

公开(公告)号：US08810039B2

公开(公告)日：2014-08-19

申请号：US13323454

申请日：2011-12-12

Applicant: Koji Takemura ,  Hiroshige Hirano ,  Masao Takahashi ,  Hikari Sano ,  Yutaka Itoh ,  Koji Koike

Inventor： Koji Takemura ,  Hiroshige Hirano ,  Masao Takahashi ,  Hikari Sano ,  Yutaka Itoh ,  Koji Koike

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/66

CPC classification number: H01L24/05 ,  H01L22/32 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.

Abstract translation: 半导体器件包括：半导体衬底; 形成在半导体衬底上的第一层间绝缘膜; 形成在第一层间绝缘膜上方的焊盘; 以及在位于所述垫下方的所述第一层间绝缘膜的部分中彼此间隔开的多个第一互连。 在焊盘下面，第一互连以四边形的平面形状形成。

公开(公告)号：US08519514B2

公开(公告)日：2013-08-27

申请号：US12923713

申请日：2010-10-05

Applicant: Seiya Fujii

Inventor： Seiya Fujii

IPC: H01L29/40

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05094 ,  H01L2224/05096 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01037 ,  H01L2924/01055 ,  H01L2924/01084 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A semiconductor device includes a substrate, at least one via hole provided on the substrate, a through silicon via provided in the at least one via hole, and an interface chip that is electrically connected to the core chips through the through silicon via. The via hole includes a bowing shaped portion in which a diameter of a center portion is larger than diameters of both edges.

Abstract translation: 半导体器件包括衬底，设置在衬底上的至少一个通孔，设置在至少一个通孔中的贯通硅通孔，以及通过硅通孔电连接到芯片的接口芯片。 通孔包括弯曲部分，其中心部分的直径大于两个边缘的直径。

公开(公告)号：US20120153458A1

公开(公告)日：2012-06-21

申请号：US12970464

申请日：2010-12-16

Applicant: Gregory Eric Howard ,  Patrick Thompson

Inventor： Gregory Eric Howard ,  Patrick Thompson

IPC: H01L23/488 ,  H01L21/768

CPC classification number: H01L24/05 ,  H01L23/528 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An integrated circuit (IC) device includes an electromigration resistant feed line. The IC device includes a substrate including active circuitry. A back end of the line (BEOL) metallization stack includes an interconnect metal layer that is coupled to a bond pad by the EM resistant feed line. A bonding feature is on the bond pad. The feed line includes a uniform portion and patterned trace portion that extends to the bond pad which includes at least three sub-traces that are electrically in parallel. The sub-traces are sized so that a number of squares associated with each of the sub-traces are within a range of a mean number of squares for the sub-traces plus or minus twenty percent or a current density provided to the bonding feature through each sub-trace is within a range of a mean current density provided to the bonding feature plus or minus twenty percent.

Abstract translation: 集成电路（IC）装置包括电迁移馈电线。 IC器件包括包括有源电路的衬底。 线的后端（BEOL）金属化堆叠包括互连金属层，其通过EM抗性馈送线耦合到接合焊盘。 接合焊盘上粘接特性。 馈送线包括均匀部分和图案化的迹线部分，其延伸到接合焊盘，其包括电并联的至少三个子迹线。 子迹线的大小使得与每个子迹线相关联的多个正方形在子迹线的平均平方根的范围内加上或减去百分之二十或者提供给粘合特征的电流密度通过 每个子迹线在提供给结合特征的平均电流密度的±20％的范围内。

公开(公告)号：US07969008B2

公开(公告)日：2011-06-28

申请号：US12163340

申请日：2008-06-27

Applicant: Kouichi Nagai

Inventor： Kouichi Nagai

IPC: H01L23/48

CPC classification number: H01L27/11507 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53295 ,  H01L24/05 ,  H01L27/11509 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05554 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A semiconductor device has: a circuit portion having semiconductor elements formed on a semiconductor substrate; insulating lamination formed above the semiconductor substrate and covering the circuit portion; a multilevel wiring structure formed in the insulating lamination and including wiring patterns and via conductors; and a pad electrode structure formed above the semiconductor substrate and connected to the multilevel wiring structure. The pad electrode structure includes pad wiring patterns and pad via conductors interconnecting the pad wiring patterns, the uppermost pad wiring pattern includes a pad pattern and a sealing pattern surrounding the pad pattern in a loop shape. Another pad wiring pattern has continuous extended pad pattern of a size overlapping the sealing pattern. The pad via conductors include a plurality of columnar via conductors disposed in register with the pad pattern and a loop-shaped wall portion disposed in register with the sealing pattern.

Abstract translation: 半导体器件具有：具有形成在半导体衬底上的半导体元件的电路部分; 形成在半导体衬底之上并覆盖电路部分的绝缘叠片; 形成在所述绝缘层叠中并且包括布线图案和通孔导体的多层布线结构; 以及形成在所述半导体衬底上并连接到所述多层布线结构的焊盘电极结构。 焊盘电极结构包括焊盘布线图案和互连焊盘布线图案的焊盘通孔导体，最上面的焊盘布线图案包括衬垫图案和围绕衬垫图案的环形形状的密封图案。 另一种衬垫布线图形具有与密封图案重叠的尺寸的连续延伸垫图形。 焊盘通孔导体包括与焊盘图案对准布置的多个柱状通孔导体和与密封图案对准设置的环形壁部分。