公开(公告)号：US20170203958A1

公开(公告)日：2017-07-20

申请号：US15119917

申请日：2015-02-05

Applicant: Robert Bosch GmbH

Inventor： Johannes CLASSEN ,  Torsten KRAMER ,  Hubert BENZEL ,  Jens FREY ,  Daniel Christoph MEISEL ,  Christoph SCHELLING

IPC: B81B7/00 ,  B81C3/00

CPC classification number: B81B7/0048 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2207/017 ,  B81C3/001 ,  B81C2201/0132 ,  B81C2201/019 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A sensor unit including a first semiconductor component and a second semiconductor component, the first semiconductor component including a first substrate and a sensor structure. The second semiconductor component includes a second substrate, the first and second semiconductor components being connected to each other with the aid of a wafer connection, the sensor unit having a decoupling structure, which is configured in such a way that the sensor structure is decoupled thermally and/or mechanically from the second semiconductor component.

公开(公告)号：US20150353343A1

公开(公告)日：2015-12-10

申请号：US14732998

申请日：2015-06-08

Applicant: Robert Bosch GmbH

Inventor： Daniel Christoph MEISEL ,  Christoph SCHELLING ,  Torsten KRAMER ,  Jens FREY

IPC: B81B7/00

CPC classification number: B81B7/007 ,  B81B2207/012 ,  B81B2207/07 ,  B81C1/00095 ,  B81C1/00238 ,  B81C2203/0792 ,  H01L23/481 ,  H01L23/522 ,  H01L24/05 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05094 ,  H01L2224/05096 ,  H01L2224/05097 ,  H01L2224/05098 ,  H01L2224/131 ,  H01L2924/1461 ,  H01L2924/01029 ,  H01L2924/014

Abstract: Measures are provided which are used for stabilizing the substructure of the connecting areas of ASIC elements. These measures relate to ASIC elements including an ASIC substrate, into which electrical circuit functions are integrated, and including an ASIC layer structure on the ASIC substrate, which includes multiple wiring levels for the circuit functions, which are separated from one another by insulation layers and are interconnected via metallic plugs. At least one connecting area for placing wire bonds or for wafer bonding is implemented in at least one of the uppermost wiring levels. At least one chain of metallic plugs arranged vertically in a direct line is implemented in the ASIC layer structure below the connecting area, which extends from the uppermost wiring level up to the ASIC substrate or oxide trenches introduced therein.

Abstract translation: 提供了用于稳定ASIC元件的连接区域的子结构的措施。 这些措施涉及ASIC元件，包括集成了电路功能的ASIC基板，并且在ASIC基板上包括ASIC层结构，其包括用于电路功能的多个布线层，它们通过绝缘层彼此分开，并且 通过金属插头互连。 用于放置线接合或用于晶片接合的至少一个连接区域在至少一个最上面的布线层中实现。 在直接布线垂直布置的至少一个金属插塞链在从连接区域下方的ASIC层结构中实现，该连接区域从最上面的布线层向上延伸到ASIC衬底或引入其中的氧化物沟槽。

公开(公告)号：US20150353345A1

公开(公告)日：2015-12-10

申请号：US14731695

申请日：2015-06-05

Applicant: Robert Bosch GmbH

Inventor： Friedjof HEUCK ,  Ralf REICHENBACH ,  Daniel Christoph MEISEL ,  Lars TEBJE ,  Mirko HATTASS ,  Jochen REINMUTH ,  Torsten KRAMER ,  Johannes CLASSEN ,  Reinhard NEUL ,  Antoine PUYGRANIER

IPC: B81B7/00

CPC classification number: B81B7/0016 ,  B81B7/0054 ,  B81B2207/017 ,  B81C2203/0785 ,  H01L2224/16225 ,  H01L2224/73253

Abstract: Method for on-chip stress decoupling to reduce stresses in a vertical hybrid integrated component including MEMS and ASIC elements and to mechanical decoupling of the MEMS structure. The MEMS/ASIC elements are mounted above each other via at least one connection layer and form a chip stack. On the assembly side, at least one connection area is formed for the second level assembly and for external electrical contacting of the component on a component support. At least one flexible stress decoupling structure is formed in one element surface between the assembly side and the MEMS layered structure including the stress-sensitive MEMS structure, in at least one connection area to the adjacent element component of the chip stack or to the component support, the stress decoupling structure being configured so that the connection material does not penetrate into the stress decoupling structure and flexibility of the stress decoupling structure is ensured.

Abstract translation: 用于片上应力去耦的方法，以减少包括MEMS和ASIC元件在内的垂直混合集成组件中的应力以及MEMS结构的机械解耦。 MEMS / ASIC元件经由至少一个连接层彼此上方安装并形成芯片堆叠。 在组装侧上，形成用于第二级组件的至少一个连接区域以及用于部件支撑件上的部件的外部电接触。 至少一个柔性应力解耦结构形成在组件侧和MEMS分层结构之间的一个元件表面中，包括应力敏感MEMS结构，至少与芯片堆叠的相邻元件部件的连接区域或组件支撑件 应力解耦结构被构造成使得连接材料不会渗透到应力解耦结构中，并且确保了应力解耦结构的柔性。