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    SLT Integrated Circuit Capacitor Structure and Methods
    4.
    发明公开
    SLT Integrated Circuit Capacitor Structure and Methods 审中-公开

    公开(公告)号：US20230361135A1

    公开(公告)日：2023-11-09

    申请号：US18313826

    申请日：2023-05-08

    申请人： pSemi Corporation

    发明人： Abhijeet Paul ,  Hiroshi Yamada ,  Alain Duvallet

    IPC分类号： H01L27/13 ,  H01L21/84 ,  H01L21/762

    CPC分类号： H01L27/13 ,  H01L21/84 ,  H01L21/76251 ,  H01L28/60

    摘要： FET IC structures that enable formation of integrated capacitors in a “flipped” SOI IC structure made using a back-side access process, such as a “single layer transfer” (SLT) process, and which eliminate or mitigate unwanted parasitic couplings to a handle wafer. In some embodiments, a conductive interconnect layer may be patterned, pre-SLT, to form an isolated first capacitor plate. In other embodiments, pre-SLT, a conductive region of the active layer of an IC may be patterned to form an isolated first capacitor plate, with one or more interconnect layers being fabricated in position to form an electrical contact to the first capacitor plate. In either case, a post-SLT top-side layer of conductive material may be patterned to form a second capacitor plate. Couplings to the resulting capacitor structures include only external connections, only internal connections, or both internal and external connections

    CIRCUIT SUBSTRATE
    8.
    发明申请
    CIRCUIT SUBSTRATE 有权

    公开(公告)号：US20230074191A1

    公开(公告)日：2023-03-09

    申请号：US17985957

    申请日：2022-11-14

    申请人： Japan Display Inc.

    发明人： Tetsuo MORITA ,  Hiroyuki KIMURA ,  Makoto SHIBUSAWA ,  Hiroshi TABATAKE ,  Yasuhiro OGAWA

    IPC分类号： H01L27/12 ,  H01L27/13 ,  H01L29/786 ,  G02F1/1362

    摘要： Provided is a display device including: a capacitor having a first electrode, a first insulating film over the first electrode, and a second electrode over the first insulating film; and a first transistor over the capacitor. The first transistor includes the second electrode, a second insulating film over the second electrode, an oxide semiconductor film over the second insulating film, and a first source electrode and a first drain electrode over the oxide semiconductor film. The first source electrode and the first drain electrode are electrically connected to the oxide semiconductor film.

    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220406934A1

    公开(公告)日：2022-12-22

    申请号：US17875376

    申请日：2022-07-27

    申请人： Kioxia Corporation

    发明人： Yuta SATO ,  Tomomasa UEDA ,  Nobuyoshi SAITO ,  Keiji IKEDA

    IPC分类号： H01L29/78 ,  H01L27/12 ,  H01L27/13 ,  H01L29/24

    摘要： A semiconductor device of an embodiment includes a substrate, a first electrode, a second electrode, the first electrode provided between the substrate and the second electrode, the oxide semiconductor layer in contact with the first electrode, an oxide semiconductor layer between the first electrode and the second electrode, the oxide semiconductor layer contains Zn and at least one first element selected from In, Ga, Si, Al, and Sn; a conductive layer between the oxide semiconductor layer and the second electrode, the conductive layer in contact with the second electrode, the conductive layer contains O and at least one second element selected from the group consisting of In, Ga, Si, Al, Sn, Zn, and Ti, a gate electrode; and a gate insulating layer between the oxide semiconductor layer and the gate electrode.

    Array of vertical transistors and method used in forming an array of vertical transistors
    10.
    发明授权
    Array of vertical transistors and method used in forming an array of vertical transistors 有权

    公开(公告)号：US11488981B2

    公开(公告)日：2022-11-01

    申请号：US16934607

    申请日：2020-07-21

    申请人： Micron Technology, Inc.

    发明人： Yi Fang Lee ,  Jaydip Guha ,  Lars P. Heineck ,  Kamal M. Karda ,  Si-Woo Lee ,  Terrence B. McDaniel ,  Scott E. Sills ,  Kevin J. Torek ,  Sheng-Wei Yang

    IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L27/13

    摘要： An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.