公开(公告)号：US11158642B2

公开(公告)日：2021-10-26

申请号：US15893323

申请日：2018-02-09

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Carl Sebastian Morandi ,  Susan Trolier-McKinstry ,  Kezhakkedath Ramunni Udayakumar ,  John Anthony Rodriguez ,  Bhaskar Srinivasan

IPC分类号： H01L27/108 ,  H01L27/11507 ,  H01L49/02

摘要： In some examples, a system comprises a capacitor including a first plate, a second plate, and a ferroelectric material disposed between the first and the second plates and comprising a Bismuth Metal Oxide-Based Lead Titanate thin film. The capacitor further comprises a dielectric layer disposed on a transistor, wherein the capacitor is disposed on the dielectric layer.

公开(公告)号：US10608075B2

公开(公告)日：2020-03-31

申请号：US16240194

申请日：2019-01-04

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Bhaskar Srinivasan ,  Guru Mathur ,  Stephen Arlon Meisner ,  Shih Chang Chang ,  Corinne Ann Gagnet

IPC分类号： H01L49/02 ,  H01L27/108 ,  H01L29/66 ,  H01L27/06 ,  H01L29/16 ,  H01L21/02 ,  H01L21/768 ,  H01L21/027 ,  H01L21/3213 ,  H01L23/532 ,  H01L23/522 ,  H01L29/94

摘要： An integrated circuit includes a capacitor located over a semiconductor substrate. The capacitor includes a first conductive layer having a first lateral perimeter, and a second conductive layer having a second smaller lateral perimeter. A first dielectric layer is located between the second conductive layer and the first conductive layer. The first dielectric layer has a thinner portion having the first lateral perimeter and a thicker portion having the second lateral perimeter. An interconnect line is located over the substrate, and includes a third conductive layer that is about coplanar with and has about a same thickness as the first conductive layer. A second dielectric layer is located over the third conductive layer. The second dielectric layer is about coplanar with and has about a same thickness as the thinner portion of the first dielectric layer.

公开(公告)号：US10177215B1

公开(公告)日：2019-01-08

申请号：US15793690

申请日：2017-10-25

申请人： Texas Instruments Incorporated

发明人： Bhaskar Srinivasan ,  Guru Mathur ,  Stephen Arlon Meisner ,  Shih Chang Chang ,  Corinne Ann Gagnet

IPC分类号： H01L49/02 ,  H01L27/108 ,  H01L29/66 ,  H01L27/06 ,  H01L29/16 ,  H01L21/02 ,  H01L21/768 ,  H01L29/94

摘要： A microelectronic device includes a capacitor having a lower plate of interconnect metal, a capacitor dielectric layer with a lower silicon dioxide layer, a silicon oxy-nitride layer, and an upper silicon dioxide layer, and an upper plate over the capacitor dielectric layer. The silicon oxy-nitride layer has an average index of refraction of 1.85 to 1.95 at a wavelength of 248 nanometers. To form the microelectronic device, the lower silicon dioxide layer, the silicon oxy-nitride layer, and the upper silicon dioxide layer are formed in sequence over an interconnect metal layer. The upper plate is formed, leaving the lower silicon dioxide layer, the silicon oxy-nitride layer, and at least a portion of the upper silicon dioxide layer over the interconnect metal layer. An interconnect mask is formed of photoresist over the upper plate and the silicon oxy-nitride layer, using the silicon oxy-nitride layer as an anti-reflection layer.

公开(公告)号：US09305998B2

公开(公告)日：2016-04-05

申请号：US14175838

申请日：2014-02-07

申请人： Texas Instruments Incorporated

发明人： Bhaskar Srinivasan ,  Eric H. Warninghoff ,  Alan Merriam ,  Haowen Bu ,  Brian E. Goodlin ,  Manoj K. Jain

IPC分类号： H01L21/00 ,  H01L49/02 ,  H01L21/02 ,  C23C16/02 ,  C23C16/40 ,  H01L27/115

CPC分类号： H01L28/75 ,  C23C16/0281 ,  C23C16/409 ,  H01L21/02197 ,  H01L21/02271 ,  H01L21/02304 ,  H01L27/11502 ,  H01L28/55

摘要： Deposition of lead-zirconium-titanate (PZT) ferroelectric material over iridium metal, in the formation of a ferroelectric capacitor in an integrated circuit. The capacitor is formed by the deposition of a lower conductive plate layer having iridium metal as a top layer. The surface of the iridium metal is thermally oxidized, prior to or during the deposition of the PZT material. The resulting iridium oxide at the surface of the iridium metal is very thin, on the order of a few nanometers, which allows the deposited PZT to nucleate according to the crystalline structure of the iridium metal rather than that of iridium oxide. The iridium oxide is also of intermediate stoichiometry (IrO2-x), and reacts with the PZT material being deposited.

摘要翻译： 在铱金属上沉积钛酸锆（PZT）铁电材料，在集成电路中形成铁电电容器。 通过沉积具有铱金属的下导电板层作为顶层形成电容器。 铱金属的表面在PZT材料沉积之前或期间被热氧化。 在铱金属表面的所得铱氧化物非常薄，几毫米数量级，这允许沉积的PZT根据铱金属的晶体结构而不是氧化铱的晶体结构成核。 氧化铱也具有中等化学计量（IrO2-x），并与沉积的PZT材料发生反应。

公开(公告)号：US20150380635A1

公开(公告)日：2015-12-31

申请号：US14734048

申请日：2015-06-09

申请人： Texas Instruments Incorporated

发明人： Bhaskar Srinivasan ,  Sarah Emily Treece ,  YungShan Chang ,  Ollen Harvey Mullis ,  Mary Alyssa Drummond Roby

IPC分类号： H01L41/08 ,  H01L41/319 ,  C23C14/06 ,  C23C14/35 ,  C23C14/34 ,  C23C14/18 ,  H01L41/18 ,  C23C14/02

CPC分类号： H01L41/0815 ,  C23C14/0036 ,  C23C14/025 ,  C23C14/088 ,  C23C14/345 ,  C23C14/354 ,  H01L41/18 ,  H01L41/316 ,  H01L41/319

摘要： A microelectronic device containing a piezoelectric component is formed sputtering an adhesion layer of titanium on a substrate by an ionized metal plasma (IMP) process. The adhesion layer is oxidized so that at least a portion of the titanium is converted to a layer of substantially stoichiometric titanium dioxide (TiO2) at a top surface of the adhesion layer. A layer of platinum is formed on the titanium dioxide of the adhesion layer; the layer of platinum has a (111) crystal orientation and an X-ray rocking curve FWHM value of less than 3 degrees. A layer of piezoelectric material is formed on the layer of platinum. The piezoelectric material may include lead zirconium titanate.

摘要翻译： 通过电离金属等离子体（IMP）工艺，在衬底上形成含有压电元件的微电子器件溅射钛的粘附层。 粘附层被氧化，使得至少一部分钛在粘合层的顶表面处转化为基本上化学计量的二氧化钛（TiO 2）层。 在粘合层的二氧化钛上形成铂层; 铂层具有（111）晶体取向和X射线摇摆曲线FWHM值小于3度。 在铂层上形成一层压电材料。 压电材料可以包括钛酸铅锆。

公开(公告)号：US20140227805A1

公开(公告)日：2014-08-14

申请号：US14175838

申请日：2014-02-07

申请人： Texas Instruments Incorporated

发明人： Bhaskar Srinivasan ,  Eric H. Warninghoff ,  Alan Merriam ,  Haowen Bu ,  Brian E. Goodlin ,  Manoj K. Jain

IPC分类号： H01L49/02

CPC分类号： H01L28/75 ,  C23C16/0281 ,  C23C16/409 ,  H01L21/02197 ,  H01L21/02271 ,  H01L21/02304 ,  H01L27/11502 ,  H01L28/55

摘要： Deposition of lead-zirconium-titanate (PZT) ferroelectric material over iridium metal, in the formation of a ferroelectric capacitor in an integrated circuit. The capacitor is formed by the deposition of a lower conductive plate layer having iridium metal as a top layer. The surface of the iridium metal is thermally oxidized, prior to or during the deposition of the PZT material. The resulting iridium oxide at the surface of the iridium metal is very thin, on the order of a few nanometers, which allows the deposited PZT to nucleate according to the crystalline structure of the iridium metal rather than that of iridium oxide. The iridium oxide is also of intermediate stoichiometry (IrO2-x), and reacts with the PZT material being deposited.

摘要翻译： 在铱金属上沉积钛酸锆（PZT）铁电材料，在集成电路中形成铁电电容器。 通过沉积具有铱金属的下导电板层作为顶层形成电容器。 铱金属的表面在PZT材料沉积之前或期间被热氧化。 在铱金属表面的所得铱氧化物非常薄，几毫米数量级，这允许沉积的PZT根据铱金属的晶体结构而不是氧化铱的晶体结构成核。 氧化铱也具有中等化学计量（IrO2-x），并与沉积的PZT材料发生反应。

公开(公告)号：US12027515B2

公开(公告)日：2024-07-02

申请号：US17490950

申请日：2021-09-30

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Yanbiao Pan ,  Robert Martin Higgins ,  Bhaskar Srinivasan ,  Pushpa Mahalingam

IPC分类号： H01L27/06 ,  H01L21/285 ,  H01L49/02

CPC分类号： H01L27/0629 ,  H01L21/28525 ,  H01L21/28556 ,  H01L28/20

摘要： Apparatus, and their methods of manufacture, that include an insulating feature above a substrate and a resistor formed on the insulating feature. Forming the resistor includes depositing polysilicon and doping the polysilicon (e.g., in-situ) with a carbon dopant and/or an oxygen dopant.

公开(公告)号：US12002846B2

公开(公告)日：2024-06-04

申请号：US17500096

申请日：2021-10-13

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Poornika Fernandes ,  David Matthew Curran ,  Stephen Arlon Meisner ,  Bhaskar Srinivasan ,  Guruvayurappan S. Mathur ,  Scott William Jessen ,  Shih Chang Chang ,  Russell Duane Fields ,  Thomas Terrance Lynch

IPC分类号： H01L21/02 ,  H01L49/02

CPC分类号： H01L28/60 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274

摘要： In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

公开(公告)号：US20230112644A1

公开(公告)日：2023-04-13

申请号：US17490950

申请日：2021-09-30

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Yanbiao Pan ,  Robert Martin Higgins ,  Bhaskar Srinivasan ,  Pushpa Mahalingam

IPC分类号： H01L27/06 ,  H01L49/02 ,  H01L21/285

摘要： Apparatus, and their methods of manufacture, that include an insulating feature above a substrate and a resistor formed on the insulating feature. Forming the resistor includes depositing polysilicon and doping the polysilicon (e.g., in-situ) with a carbon dopant and/or an oxygen dopant.

公开(公告)号：US20210327802A1

公开(公告)日：2021-10-21

申请号：US17360183

申请日：2021-06-28

申请人： Texas Instruments Incorporated

发明人： Mona M. Eissa ,  Umamaheswari Aghoram ,  Pushpa Mahalingam ,  Erich Wesley Kinder ,  Bhaskar Srinivasan ,  Brian E. Goodlin

IPC分类号： H01L23/522 ,  H01L49/02 ,  H01L21/768

摘要： An integrated circuit (IC) includes a semiconductor surface layer of a substrate including circuitry formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal (MIM) capacitor. A multi-layer metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer is over the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, wherein the trench is lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer is over the filled trench. A filled via through the second ILD layer provides a connection to the top capacitor plate.