公开(公告)号：US12218190B2

公开(公告)日：2025-02-04

申请号：US17731510

申请日：2022-04-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei Sadovnikov ,  Guruvayurappan S. Mathur

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/78

Abstract: A method of manufacturing an integrated circuit includes forming first and second false collector regions of a first conductivity type adjacent to a surface of an epitaxial layer of semiconductor material. The first false collector region is located laterally on a first side of a base region. The base region is formed within the epitaxial layer and has a second conductivity type. The second false collector region is located laterally on a second side of the base region. The second side is opposite the first side of the base region. The base region is a base of a parasitic bipolar junction in an isolation region of an active semiconductor device.

公开(公告)号：US20230317775A1

公开(公告)日：2023-10-05

申请号：US17731510

申请日：2022-04-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei Sadovnikov ,  Guruvayurappan S. Mathur

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0623 ,  H01L21/76202 ,  H01L21/76232 ,  H01L29/063 ,  H01L29/7823

Abstract: A method of manufacturing an integrated circuit includes forming first and second false collector regions of a first conductivity type adjacent to a surface of an epitaxial layer of semiconductor material. The first false collector region is located laterally on a first side of a base region. The base region is formed within the epitaxial layer and has a second conductivity type. The second false collector region is located laterally on a second side of the base region. The second side is opposite the first side of the base region. The base region is a base of a parasitic bipolar junction in an isolation region of an active semiconductor device.

公开(公告)号：US12015054B2

公开(公告)日：2024-06-18

申请号：US17710320

申请日：2022-03-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei Sadovnikov ,  Guruvayurappan S. Mathur

IPC: H01L29/06 ,  H01L21/265 ,  H01L21/761 ,  H01L29/66 ,  H01L29/73

CPC classification number: H01L29/0619 ,  H01L21/26513 ,  H01L21/761 ,  H01L29/66234 ,  H01L29/73

Abstract: A method includes implanting dopant of a first conductivity type into an epitaxial layer of semiconductor material to form first and second false collector regions adjacent to the surface of the epitaxial layer. The first false collector region is located laterally on a first side of a base region. The base region is formed within the epitaxial layer from dopant of a second conductivity type that is opposite the first conductivity type. The second false collector region is located laterally on a second side of the base region. The second side is opposite the first side of the base region. The base region is a base of a parasitic bipolar junction in an isolation region of an active semiconductor device.

公开(公告)号：US12002846B2

公开(公告)日：2024-06-04

申请号：US17500096

申请日：2021-10-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika Fernandes ,  David Matthew Curran ,  Stephen Arlon Meisner ,  Bhaskar Srinivasan ,  Guruvayurappan S. Mathur ,  Scott William Jessen ,  Shih Chang Chang ,  Russell Duane Fields ,  Thomas Terrance Lynch

IPC: H01L21/02 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274

Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

公开(公告)号：US20250048656A1

公开(公告)日：2025-02-06

申请号：US18228338

申请日：2023-07-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jack Qian ,  Kemal Tamer San ,  Guruvayurappan S. Mathur

IPC: H10B99/00 ,  H10B20/20

Abstract: Described examples include an integrated circuit having a plurality of nominally identical polycrystalline silicon resistors over a semiconductor substrate. Each of the polysilicon resistors has a resistor body with a first end and a second end, wherein the first end is connected to a current source and the second end is connected to a resistance discriminator. A first proper subset of the resistors have a first resistance, and a second first proper subset of the resistors have a difference second resistance.

公开(公告)号：US12170310B2

公开(公告)日：2024-12-17

申请号：US16453796

申请日：2019-06-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Guruvayurappan S. Mathur ,  Abbas Ali ,  Poornika Fernandes ,  Bhaskar Srinivasan ,  Darrell R. Krumme ,  Joao Sergio Afonso ,  Shih-Chang Chang ,  Shariq Arshad

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/06 ,  H01L49/02

Abstract: In some examples, an integrated circuit includes an isolation layer disposed on or over a semiconductor substrate. The integrated circuit also includes a first conductive plate located over the isolation layer and a composite dielectric layer located over the first conductive plate. The composite dielectric layer includes a first sublayer comprising a first chemical composition; a second sublayer comprising a second different chemical composition; and a third sublayer comprising a third chemical composition substantially similar to the first chemical composition. The integrated circuit further includes a second conductive plate located directly on the composite dielectric layer above the first conductive plate.

公开(公告)号：US11171200B2

公开(公告)日：2021-11-09

申请号：US16584463

申请日：2019-09-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika Fernandes ,  David Matthew Curran ,  Stephen Arion Meisner ,  Bhaskar Srinivasan ,  Guruvayurappan S. Mathur ,  Scott William Jessen ,  Shih Chang Chang ,  Russell Duane Fields ,  Thomas Terrance Lynch

IPC: H01L49/02 ,  H01L21/02

Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

公开(公告)号：US20240290831A1

公开(公告)日：2024-08-29

申请号：US18658333

申请日：2024-05-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei Sadovnikov ,  Guruvayurappan S. Mathur

IPC: H01L29/06 ,  H01L21/265 ,  H01L21/761 ,  H01L29/66 ,  H01L29/73

CPC classification number: H01L29/0619 ,  H01L21/26513 ,  H01L21/761 ,  H01L29/66234 ,  H01L29/73

Abstract: A method includes implanting dopant of a first conductivity type into an epitaxial layer of semiconductor material to form first and second false collector regions adjacent to the surface of the epitaxial layer. The first false collector region is located laterally on a first side of a base region. The base region is formed within the epitaxial layer from dopant of a second conductivity type that is opposite the first conductivity type. The second false collector region is located laterally on a second side of the base region. The second side is opposite the first side of the base region. The base region is a base of a parasitic bipolar junction in an isolation region of an active semiconductor device.

公开(公告)号：US11605587B2

公开(公告)日：2023-03-14

申请号：US16383176

申请日：2019-04-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika Fernandes ,  Bhaskar Srinivasan ,  Scott William Jessen ,  Guruvayurappan S. Mathur

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/311

Abstract: In some examples, a method comprises: obtaining a substrate having at a metal interconnect layer deposited over the substrate; forming a first dielectric layer on the metal interconnect layer; forming a second dielectric layer on the first dielectric layer; forming a capacitor metal layer on the second dielectric layer; patterning and etching the capacitor metal layer and the second dielectric layer to the first dielectric layer to leave a portion of the capacitor metal layer and the second dielectric layer on the first dielectric layer; forming an anti-reflective coating to cover the portion of the capacitor metal layer and the second dielectric layer, and to cover the metal interconnect layer; and patterning the metal interconnect layer to form a first metal layer and a second metal layer.

公开(公告)号：US11587864B2

公开(公告)日：2023-02-21

申请号：US17540447

申请日：2021-12-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika Fernandes ,  Ye Shao ,  Guruvayurappan S. Mathur ,  John K. Arch ,  Paul Stulik

IPC: H01L21/00 ,  H01L23/522 ,  H01G15/00 ,  H01G4/06

Abstract: An integrated circuit (IC) includes a substrate and a first capacitor on the substrate. The first capacitor has a first width. A first dielectric layer is provided on a side of the first capacitor opposite the substrate. Further, a second capacitor is present on a side of the first dielectric layer opposite the first capacitor. The second capacitor has a second width that is smaller than the first width. The IC also has a second dielectric layer and a first metal layer. The second dielectric layer is on a side of the second capacitor opposite the first dielectric layer. The first metal layer is on a side of the second dielectric layer opposite the second capacitor.