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公开(公告)号：US20240113102A1
公开(公告)日：2024-04-04
申请号：US17957931
申请日：2022-09-30
CPC分类号： H01L27/0629 , H01L29/66181 , H01L29/945
摘要： A microelectronic device includes a buried trench capacitor below an electronic component of the microelectronic device. In one embodiment, the buried trench capacitor may be formed between a silicon oxide capped p-type buried trench capacitor polysilicon region and a buried trench capacitor deep n-type region separated by buried trench capacitor liner dielectric. In a second embodiment, the buried trench capacitor may be formed by a buried trench capacitor polysilicon region and a p-type silicon epitaxial region separated by a buried trench capacitor liner dielectric. One terminal of the deep trench capacitor is made through the substrate via a deep trench substrate contact. The second terminal of the deep trench capacitor is made via a well contact that connects to the capacitor through a deep well region in one embodiment and through a polysilicon layer in a second embodiment.
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公开(公告)号：US11869986B2
公开(公告)日：2024-01-09
申请号：US17459991
申请日：2021-08-27
IPC分类号： H01L29/866 , H01L27/02 , H01L29/66
CPC分类号： H01L29/866 , H01L27/0255 , H01L29/66106 , H01L27/0259
摘要： A semiconductor device which includes two or more integrated deep trench features configured as a Zener diode. The Zener diode includes a plurality of deep trenches extending into semiconductor material of the substrate and a dielectric deep trench liner that includes a dielectric material. The deep trench further includes a doped sheath contacting the deep trench liner and an electrically conductive deep trench filler material within the deep trench. The doped sheath of adjacent deep trenches overlap and form a region of higher doping concentration which sets the breakdown voltage of the Zener diode. The Zener diode can be used as a triggering diode to limit the voltage on other components in a semiconductor device.
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公开(公告)号：US10593773B2
公开(公告)日：2020-03-17
申请号：US15720616
申请日：2017-09-29
IPC分类号： H01L29/423 , H01L21/02 , H01L29/221 , H01L29/66 , H01L29/78 , H01L29/06 , H01L21/762 , H01L29/40 , H01L21/761 , H01L29/10
摘要： A laterally diffused metal oxide silicon (LDMOS) transistor and a method of making the LDMOS transistor are disclosed. The LDMOS transistor includes a drain drift region formed in a substrate and containing a drain contact region. A gate structure overlies a channel region in the substrate and a first shallow-trench isolation (STI) structure is formed between the drain contact region and the channel region. The first STI structure contains a high-k dielectric and a second STI structure contains silicon dioxide.
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公开(公告)号：US20240038580A1
公开(公告)日：2024-02-01
申请号：US17877976
申请日：2022-07-31
发明人： Hao Yang , Asad Haider , Guruvayurappan Mathur , Abbas Ali , Alexei Sadovnikov , Umamaheswari Aghoram
IPC分类号： H01L21/762 , H01L29/06
CPC分类号： H01L21/76229 , H01L29/0623
摘要： An electronic device includes a semiconductor substrate and a semiconductor surface layer having a first conductivity type, the semiconductor surface layer over the semiconductor substrate and having a top surface, a buried layer having an opposite second conductivity type between the semiconductor surface layer and the semiconductor substrate, a dielectric isolation layer that extends over and into the semiconductor surface layer, a deep trench structure that extends through the dielectric isolation layer into the semiconductor surface layer, and a silicide blocking layer on a top surface of the deep trench structure.
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公开(公告)号：US11616011B2
公开(公告)日：2023-03-28
申请号：US17360183
申请日：2021-06-28
发明人： Mona M. Eissa , Umamaheswari Aghoram , Pushpa Mahalingam , Erich Wesley Kinder , Bhaskar Srinivasan , Brian E. Goodlin
IPC分类号： H01L23/522 , H01L49/02 , H01L21/768
摘要： An integrated circuit (IC) includes a semiconductor surface layer of a substrate including circuitry formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal (MIM) capacitor. A multi-layer metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer is over the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, wherein the trench is lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer is over the filled trench. A filled via through the second ILD layer provides a connection to the top capacitor plate.
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公开(公告)号：US20210074630A1
公开(公告)日：2021-03-11
申请号：US16564849
申请日：2019-09-09
发明人： Mona M. Eissa , Umamaheswari Aghoram , Pushpa Mahalingam , Erich Wesley Kinder , Bhaskar Srinivasan , Brian E. Goodlin
IPC分类号： H01L23/522 , H01L49/02 , H01L21/768
摘要： An integrated circuit (IC) includes a semiconductor surface layer of a substrate including circuitry formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal (MIM) capacitor. A multi-layer metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer is over the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, wherein the trench is lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer is over including the filled trench. A filled via through the second ILD layer provides a contact to a top plate contact on the top capacitor plate.
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7.发明公开公开(公告)号：US20240038579A1
公开(公告)日：2024-02-01
申请号：US17877964
申请日：2022-07-31
发明人： Asad Haider , Hao Yang , Guruvayurappan Mathur , Alexei Sadovnikov , Abbas Ali , Umamaheswari Aghoram
IPC分类号： H01L21/762 , H01L29/06
CPC分类号： H01L21/76229 , H01L29/0623
摘要： An electronic device includes a semiconductor substrate and a semiconductor surface layer having a first conductivity type, as well as a buried layer, a deep trench structure and a shallow trench isolation structure, the semiconductor surface layer over the semiconductor substrate and having a top surface, the buried layer having an opposite second conductivity type between the semiconductor surface layer and the semiconductor substrate, the deep trench structure including a trench that extends through the semiconductor surface layer and into the buried layer, a dielectric liner on a sidewall of the trench from the semiconductor surface layer to the buried layer, and polysilicon that extends on the dielectric liner and fills the trench to the side of the semiconductor surface layer, the shallow trench isolation structure extends into the semiconductor surface layer, and the shallow trench isolation structure in contact with the deep trench structure.
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公开(公告)号：US10651039B2
公开(公告)日：2020-05-12
申请号：US15858515
申请日：2017-12-29
IPC分类号： H01L21/28 , H01L21/321 , H01L21/285 , H01L29/423 , H01L29/49 , H01L29/66 , H01L21/02
摘要： A method of forming a semiconductor device includes forming source regions and drain regions in a semiconductor substrate, and a gate electrode over said semiconductor substrate and between said source and drain regions. The gate electrode is formed from a first semiconductor gate electrode layer deposited on said gate dielectric layer at a first substrate temperature. A second semiconductor gate electrode layer is deposited on the first semiconductor gate electrode layer at a second substrate temperature greater than said first temperature. The two gate electrode layers may be annealed to form a homogenous polycrystalline layer with improved grain size distribution, thereby improving transistor matching in a semiconductor device.
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9.发明公开公开(公告)号：US20240088305A1
公开(公告)日：2024-03-14
申请号：US18514413
申请日：2023-11-20
IPC分类号： H01L29/866 , H01L27/02 , H01L29/66
CPC分类号： H01L29/866 , H01L27/0255 , H01L29/66106 , H01L27/0259
摘要： A semiconductor device which includes two or more integrated deep trench features configured as a Zener diode. The Zener diode includes a plurality of deep trenches extending into semiconductor material of the substrate and a dielectric deep trench liner that includes a dielectric material. The deep trench further includes a doped sheath contacting the deep trench liner and an electrically conductive deep trench filler material within the deep trench. The doped sheath of adjacent deep trenches overlap and form a region of higher doping concentration which sets the breakdown voltage of the Zener diode. The Zener diode can be used as a triggering diode to limit the voltage on other components in a semiconductor device.
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公开(公告)号：US20230066563A1
公开(公告)日：2023-03-02
申请号：US17459991
申请日：2021-08-27
IPC分类号： H01L29/866 , H01L27/02 , H01L29/66
摘要： A semiconductor device which includes two or more integrated deep trench features configured as a Zener diode. The Zener diode includes a plurality of deep trenches extending into semiconductor material of the substrate and a dielectric deep trench liner that includes a dielectric material. The deep trench further includes a doped sheath contacting the deep trench liner and an electrically conductive deep trench filler material within the deep trench. The doped sheath of adjacent deep trenches overlap and form a region of higher doping concentration which sets the breakdown voltage of the Zener diode. The Zener diode can be used as a triggering diode to limit the voltage on other components in a semiconductor device.
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