公开(公告)号：US20150103494A1

公开(公告)日：2015-04-16

申请号：US14513436

申请日：2014-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hee-jeong Kim ,  Eun-Chul AHN ,  Yong-Kwan LEE

IPC: H05K1/11 ,  H05K1/18 ,  H05K1/09

CPC classification number: H05K3/24 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/18161 ,  H05K2201/10674 ,  H05K2203/049 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Printed circuit boards are provided. The printed circuit board includes an insulation layer, an interconnection portion and a metal layer. The insulation layer has a flat plate shape and includes a top surface and a bottom surface. The interconnection portion is disposed on at least one of the top and bottom surfaces of the insulation layer. The interconnection portion includes a plurality of interconnection patterns. The metal layer covers the plurality of interconnection patterns of the interconnection portion. Related semiconductor packages are also provided.

Abstract translation: 提供印刷电路板。 印刷电路板包括绝缘层，互连部分和金属层。 绝缘层具有平板形状并且包括顶表面和底表面。 互连部分设置在绝缘层的顶表面和底表面中的至少一个上。 互连部分包括多个互连图案。 金属层覆盖互连部分的多个互连图案。 还提供了相关的半导体封装。

公开(公告)号：US20130148310A1

公开(公告)日：2013-06-13

申请号：US13706645

申请日：2012-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Kwan LEE

IPC: H05K1/02 ,  H01L25/00

CPC classification number: H05K1/0298 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/16 ,  H01L25/00 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/02 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/099

Abstract: A printed circuit board (PCB) includes a wire pattern having first and second surfaces facing in opposite directions from each other, the wire pattern including a first region having a first thickness and a second region having a second thickness greater than the first thickness; a core insulation layer on the second surface in the first region, the core insulation layer having a third surface adjacent to the second surface in the first region and a fourth surface facing in an opposite direction from the third surface, the fourth surface being connected to the second surface; and a first protection layer covering a portion of the fourth surface of the core insulation layer and a portion of the second surface in the second region.

Abstract translation: 印刷电路板（PCB）包括具有彼此面向相反方向的第一和第二表面的线图案，该线图案包括具有第一厚度的第一区域和具有大于第一厚度的第二厚度的第二区域; 在第一区域的第二表面上的芯绝缘层，芯绝缘层具有与第一区域中的第二表面相邻的第三表面和与第三表面相反的第四表面，第四表面连接到 第二表面 以及覆盖所述芯绝缘层的第四表面的一部分和所述第二区域中的所述第二表面的一部分的第一保护层。

公开(公告)号：US20180076105A1

公开(公告)日：2018-03-15

申请号：US15641288

申请日：2017-07-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Baek KI ,  Tark-Hyun KO ,  Kun-Dae YEOM ,  Yong-Kwan LEE ,  Keun-Ho JANG

IPC: H01L23/10 ,  H01L23/057 ,  H01L23/00

CPC classification number: H01L23/10 ,  H01L21/561 ,  H01L21/565 ,  H01L23/057 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1412 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15151 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01049 ,  H01L2924/00014

Abstract: A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.

公开(公告)号：US20190295909A1

公开(公告)日：2019-09-26

申请号：US16441591

申请日：2019-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Baek KI ,  Tark-Hyun KO ,  Kun-Dae YEOM ,  Yong-Kwan LEE ,  Keun-Ho JANG ,  Sang Jin HYUN

IPC: H01L23/10 ,  H01L23/13 ,  H01L23/538 ,  H01L23/057 ,  H01L21/56

Abstract: A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.