公开(公告)号：US20240234371A1

公开(公告)日：2024-07-11

申请号：US18171672

申请日：2023-02-21

申请人： Unimicron Technology Corp.

发明人： John Hon-Shing Lau ,  Tzyy-Jang Tseng

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00

CPC分类号： H01L25/0655 ,  H01L23/538 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/05647 ,  H01L2224/08225 ,  H01L2224/1132 ,  H01L2224/1413 ,  H01L2224/16227 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/94 ,  H01L2924/05442

摘要： A chip package structure includes a package carrier, a plurality of chips, a bridge and a plurality of solder balls or C4 bumps. The package carrier includes a plurality of carrier pads. The chips are arranged side by side on the package carrier. Each of the chips includes a plurality of first pads and a plurality of second pads. The bridge is located between the chips and the package carrier and includes a plurality of bridge pads. Each of the first pads is hybrid bonded with each of the bridge pads to form a hybrid bonding pad, so that the chips are electrically connected to each other through the bridge. The solder balls are located between the package carrier and the chips. The second pads of each of the chips are electrically connected to the carrier pads of the package carrier through the solder balls.

公开(公告)号：US20240234228A9

公开(公告)日：2024-07-11

申请号：US18398680

申请日：2023-12-28

申请人： ROHM CO., LTD.

发明人： Kunihiro KOMIYA

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L23/50 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/3114 ,  H01L23/50 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L24/06 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0612 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14104 ,  H01L2224/1413 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107

摘要： The semiconductor device has the CSP structure and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps.

公开(公告)号：US11901251B2

公开(公告)日：2024-02-13

申请号：US17854316

申请日：2022-06-30

申请人： ROHM CO., LTD.

发明人： Kunihiro Komiya

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L23/50 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/3114 ,  H01L23/50 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L24/06 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0612 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/1413 ,  H01L2224/14104 ,  H01L2924/014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L24/13 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05144 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014

摘要： The semiconductor device has the CSP structure and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps.

公开(公告)号：US20180182701A1

公开(公告)日：2018-06-28

申请号：US15819310

申请日：2017-11-21

申请人： SHINKO ELECTRIC INDUSTRIES CO., LTD.

发明人： Kei Imafuji

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L23/49838 ,  H01L23/3157 ,  H01L23/49866 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/1413 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81464 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

摘要： A wiring board includes an insulator layer having a top surface, and a plurality of pads arranged in a pad arrangement region on the top surface of the insulator layer. The pad arrangement region includes a first region in which a first plurality of pads among the plurality of pads are arranged at a first density, and a second region in which a second plurality of pads among the plurality of pads are arranged at a second density lower than the first density. At least one dummy pad is arranged juxtaposed to at least one of the second plurality of pads in the second region of the pad arrangement region.

公开(公告)号：US20140167293A1

公开(公告)日：2014-06-19

申请号：US13830804

申请日：2013-03-14

申请人： SK HYNIX INC.

发明人： Dong-Uk LEE ,  Young-Ju KIM ,  Keun-Soo SONG

IPC分类号： H01L23/00

CPC分类号： H01L23/49811 ,  G11C7/222 ,  G11C7/225 ,  H01L23/5286 ,  H01L24/06 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/0613 ,  H01L2224/1413 ,  H01L2924/3841

摘要： An integrated circuit includes first and second bump pads spaced from each other with a first space, configured to receive differential signals for a normal operation, and at least one redundant bump pad spaced from the first bump pad with a second space smaller than the first space, configured to receive a signal for a repair to the differential signals.

公开(公告)号：US08421175B2

公开(公告)日：2013-04-16

申请号：US12556827

申请日：2009-09-10

申请人： Robert Nicol

发明人： Robert Nicol

IPC分类号： H01L31/0232

CPC分类号： H01L23/3114 ,  H01L23/481 ,  H01L23/562 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/1413 ,  H01L2224/14181 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/32054 ,  H01L2224/32227 ,  H01L2224/3315 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00

摘要： A wafer level packaged integrated circuit includes an array of contacts, a silicon layer and a glass layer. The silicon and glass layers are bonded together to form a bonding material layer therebetween. The bonding material layer includes gaps between the silicon layer and the glass layer at areas where no bonding material is present. An array of contacts is adjacent the semiconductor layer on a side thereof opposite the bonding layer. The wafer level packaged integrated circuit is provided with additional bonding material layer portions within the gaps and aligned with at least some of the contacts. When the wafer level packaged integrated circuit is configured as an image sensor or display having a pixel array, the additional bonding material layer portions are not used in an area of the pixel array.

摘要翻译： 晶圆级封装集成电路包括触点阵列，硅层和玻璃层。 硅和玻璃层结合在一起，以在它们之间形成接合材料层。 接合材料层在不存在接合材料的区域包括硅层和玻璃层之间的间隙。 触点阵列在与结合层相对的一侧与半导体层相邻。 晶片级封装集成电路在间隙内提供附加的结合材料层部分并与至少一些触点对准。 当晶片级封装集成电路被配置为具有像素阵列的图像传感器或显示器时，在像素阵列的区域中不使用附加的接合材料层部分。

公开(公告)号：US08405208B2

公开(公告)日：2013-03-26

申请号：US13365591

申请日：2012-02-03

申请人： Kunihiro Komiya

发明人： Kunihiro Komiya

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/50 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L24/06 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0612 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14104 ,  H01L2224/1413 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014

摘要： The semiconductor device has the CSP structure, and includes: a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps are arranged in two rows along the periphery of the semiconductor device. The electrode pads are arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring is extended from an electrode pad, and is connected to any one of the outermost solder bumps or any one of the inner solder bumps.

摘要翻译： 半导体器件具有CSP结构，并且包括：形成在半导体集成电路上的多个电极焊盘，用于从/从外部输入/输出信号; 用于制造外部引线电极的焊料凸块; 并重新布线。 焊料凸块沿着半导体器件的周边布置成两排。 电极焊盘配置在最外侧的焊料凸块的内部，以夹在两排焊料凸点之间。 重新布线的每个迹线从电极焊盘延伸，并且连接到任何一个最外面的焊料凸块或任何一个内部焊料凸块。

公开(公告)号：US20130062763A1

公开(公告)日：2013-03-14

申请号：US13231609

申请日：2011-09-13

申请人： Alex CHAN ,  Paul Brown

发明人： Alex CHAN ,  Paul Brown

IPC分类号： H01L23/498

CPC分类号： H01L24/14 ,  G06F17/5068 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/66 ,  H01L2223/6666 ,  H01L2224/13014 ,  H01L2224/1413 ,  H01L2224/73204 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1304 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/20648 ,  H05K1/112 ,  H05K2201/10636 ,  H05K2201/10734 ,  Y02P70/611

摘要： Embodiments of the invention place surface-mount devices such as decoupling capacitors, resistors or other devices directly on the underside of a ball grid array (BGA) electronic integrated circuit (EIC) package, in place of de-populated BGA pads.

公开(公告)号：US11791252B2

公开(公告)日：2023-10-17

申请号：US17830022

申请日：2022-06-01

申请人： Micron Technology, Inc.

发明人： Owen R. Fay ,  Jack E. Murray

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/1413 ,  H01L2224/14179 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45099 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/0652 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/48145 ,  H01L2924/00012

摘要： Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.

公开(公告)号：US20180033750A1

公开(公告)日：2018-02-01

申请号：US15727252

申请日：2017-10-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： CHANG-PIN HUANG ,  HSIEN-MING TU ,  CHING-JUNG YANG ,  SHIH-WEI LIANG ,  HUNG-YI KUO ,  YU-CHIA LAI ,  HAO-YI TSAI ,  CHUNG-SHI LIU ,  CHEN-HUA YU

IPC分类号： H01L23/00 ,  H01L23/532 ,  H01L23/522 ,  H01L21/56

CPC分类号： H01L24/05 ,  H01L21/568 ,  H01L23/5226 ,  H01L23/53228 ,  H01L24/02 ,  H01L24/13 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05015 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/12105 ,  H01L2224/13026 ,  H01L2224/1413 ,  H01L2924/18162 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/37001

摘要： A method of manufacturing a semiconductor structure include: providing a die including a die pad disposed over the die; disposing a conductive member over the die pad of the die; forming a molding surrounding the die and the conductive member; disposing a dielectric layer over the molding, the die and the conductive member; and forming an interconnect structure including a land portion and a plurality of via portions. The land portion is disposed over the dielectric layer, the plurality of via portions are disposed over the conductive member and protruded from the land portion to the conductive member through the dielectric layer, and each of the plurality of via portions at least partially contacts with the conductive member.