公开(公告)号：US20150061115A1

公开(公告)日：2015-03-05

申请号：US14013597

申请日：2013-08-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： MENG-TSE CHEN ,  HSIU-JEN LIN ,  CHIH-WEI LIN ,  MING-DA CHENG ,  CHIH-HANG TUNG ,  CHUNG-SHI LIU

IPC分类号： H01L23/00

CPC分类号： H01L24/06 ,  H01L21/56 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/0558 ,  H01L2224/05666 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/119 ,  H01L2224/11906 ,  H01L2224/13005 ,  H01L2224/13014 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on a second end of the conductive body. The conductive body has a longitudinal direction perpendicular to a surface of the contact pad. The conductive body has an average grain size (a) on a cross sectional plane (Plane A) whose normal is perpendicular to the longitudinal direction of the conductive body. The conductive layer has an average grain size (b) on Plane A. The conductive body and the conductive layer are composed of same material, and the average grain size (a) is greater than the average grain size (b).

摘要翻译： 导电互连结构包括接触垫; 在第一端连接到接触垫的导电体; 以及位于所述导电体的第二端上的导电层。 导电体具有垂直于接触垫表面的纵向方向。 导电体在垂直于导电体的纵向方向的截面（平面A）上具有平均粒径（a）。 导电层在平面A上具有平均粒径（b）。导电体和导电层由相同的材料组成，平均晶粒尺寸（a）大于平均晶粒尺寸（b）。

公开(公告)号：US20220246435A1

公开(公告)日：2022-08-04

申请号：US17727606

申请日：2022-04-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： YU-HSIANG HU ,  WEI-YU CHEN ,  HUNG-JUI KUO ,  WEI-HUNG LIN ,  MING-DA CHENG ,  CHUNG-SHI LIU

IPC分类号： H01L21/304 ,  H01L25/07 ,  H01L23/31 ,  H01L23/14 ,  H01L23/15 ,  H01L25/065 ,  H01L23/00

摘要： A method of manufacturing a semiconductor structure includes receiving a die comprising a top surface and a sacrificial layer covering the top surface; disposing a molding surrounding the die; removing the sacrificial layer from the die; disposing a polymer over the die and the molding, wherein the polymer has a first bottom surface contacting the die and a second bottom surface contacting the molding, and the first bottom surface is at a level substantially same as the second bottom surface.

公开(公告)号：US20200006208A1

公开(公告)日：2020-01-02

申请号：US16567692

申请日：2019-09-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： JIUN-YI WU ,  CHEN-HUA YU ,  CHUNG-SHI LIU ,  CHIEN HSUN LEE

IPC分类号： H01L23/498 ,  H01L23/16 ,  H01L23/00 ,  H01L23/522

摘要： A semiconductor structure includes a first die, a molding at least partially surrounding the first die, a via extended through the molding, a second die disposed over the molding, a connector dispose between the second die and the via, and an underfill at least partially surrounding the connector. The first die includes a first surface and a second surface opposite to the first surface. The second die includes a third surface facing the first die, a fourth surface opposite to the third surface, and a sidewall between the third surface and the fourth surface. The connector is in contact with the third surface of the second die and the via. The second die is electrically connected to the via. The underfill covers a portion of the sidewall of the second die and a portion of the second surface of the first die.

公开(公告)号：US20150243573A1

公开(公告)日：2015-08-27

申请号：US14192374

申请日：2014-02-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD

发明人： YU-HSIANG HU ,  WEI-YU CHEN ,  HUNG-JUI KUO ,  WEI-HUNG LIN ,  MING-DA CHENG ,  CHUNG-SHI LIU

IPC分类号： H01L23/31 ,  H01L21/304 ,  H01L21/311 ,  H01L23/29 ,  H01L21/56

CPC分类号： H01L21/304 ,  H01L21/561 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/3157 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0655 ,  H01L25/072 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244

摘要： A semiconductor structure includes a die including a top surface and a sidewall, and a molding surrounding the die and including a top surface, a sidewall interfacing with the sidewall of the die, and a curved surface including a curvature greater than zero and coupling the sidewall of the molding with the top surface of the molding.

摘要翻译： 半导体结构包括具有顶表面和侧壁的模具以及围绕模头的模制件，并且包括顶表面，与模具的侧壁相接合的侧壁以及包括大于零的曲率的曲面，并将侧壁 的模制件与模制件的顶部表面。

公开(公告)号：US20150235874A1

公开(公告)日：2015-08-20

申请号：US14183913

申请日：2014-02-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： CHEN-HUA YU ,  CHIH-FAN HUANG ,  CHUN-HUNG LIN ,  MING-DA CHENG ,  CHUNG-SHI LIU ,  MIRNG-JI LII

IPC分类号： H01L21/56 ,  G01N25/16 ,  H01L23/00 ,  H01L21/268 ,  H01L25/00

CPC分类号： H01L22/12 ,  H01L21/268 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/562 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L29/7847 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83192 ,  H01L2224/83868 ,  H01L2224/83871 ,  H01L2224/97 ,  H01L2924/0002 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2924/00014

摘要： A method includes followings operations. A substrate including a first surface and a second surface is provided. The substrate and a transparent film are heated to attach the transparent film on the first surface. A first coefficient of a thermal expansion (CTE) mismatch is between the substrate and the transparent film. The substrate and the transparent film are cooled. A polymeric material is disposed on the second surface. A second CTE mismatch is between the substrate and the polymeric material. The second CTE mismatch is counteracted by the first CTE mismatch.

摘要翻译： 一种方法包括以下操作。 提供了包括第一表面和第二表面的基板。 加热衬底和透明膜以将透明膜附着在第一表面上。 热膨胀（CTE）失配的第一系数在基片和透明薄膜之间。 将基板和透明膜冷却。 聚合材料设置在第二表面上。 第二个CTE不匹配在基材和聚合物材料之间。 第二个CTE不匹配被第一个CTE不匹配所抵消。

公开(公告)号：US20150061162A1

公开(公告)日：2015-03-05

申请号：US14013503

申请日：2013-08-29

申请人： Taiwan Semiconductor Manufacturing Company Ltd.

发明人： CHEN-HUA YU ,  MIRNG-JI LII ,  CHUNG-SHI LIU ,  CHANG-CHIA HUANG ,  CHIH-WEI LIN ,  MING-DA CHENG

IPC分类号： H01L25/065 ,  H01L23/00

CPC分类号： H01L25/0652 ,  H01L21/568 ,  H01L23/16 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2224/83 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor structure includes several operations. The several operations include placing a plurality of dies on a carrier; defining a first zone and a second zone in a top surface of the carrier; calculating a first coverage ratio in the first zone; calculating a second coverage ratio in the second zone; disposing a dummy block on a specified location of the top surface of the carrier if the difference between the first coverage ratio and the second coverage ratio is greater than a predetermined value; forming a molding compound on the carrier.

摘要翻译： 制造半导体结构的方法包括若干操作。 这些操作包括将多个管芯放置在载体上; 在载体的顶表面中限定第一区和第二区; 计算第一区域中的第一覆盖率; 计算第二区域的第二覆盖率; 如果所述第一覆盖率和所述第二覆盖率之间的差大于预定值，则在所述载波的顶表面的指定位置处布置虚拟块; 在载体上形成模塑料。

公开(公告)号：US20190115313A1

公开(公告)日：2019-04-18

申请号：US16229585

申请日：2018-12-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： ALEXANDER KALNITSKY ,  YI-YANG LEI ,  HSI-CHING WANG ,  CHENG-YU KUO ,  TSUNG LUNG HUANG ,  CHING-HUA HSIEH ,  CHUNG-SHI LIU ,  CHEN-HUA YU ,  CHIN-YU KU ,  DE-DUI LIAO ,  KUO-CHIO LIU ,  KAI-DI WU ,  KUO-PIN CHANG ,  SHENG-PIN YANG ,  ISAAC HUANG

IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L21/683

CPC分类号： H01L24/83 ,  H01L21/6835 ,  H01L21/78 ,  H01L24/03 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/83201 ,  H01L2224/8385 ,  H01L2224/921 ,  H01L2224/94 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/014

摘要： A method of manufacturing a semiconductor structure includes receiving a first substrate including an IMD layer disposed over the first substrate and a plurality of conductive bumps disposed in the IMD layer; receiving a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the IMD layer is exposed through the patterned adhesive; and bonding the first substrate with the second substrate, wherein a top surface of the at least portion of the IMD layer is exposed through the patterned adhesive after bonding the first substrate with the second substrate.

公开(公告)号：US20160365332A1

公开(公告)日：2016-12-15

申请号：US14738109

申请日：2015-06-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： ALEXANDER KALNITSKY ,  YI-YANG LEI ,  HSI-CHING WANG ,  CHENG-YU KUO ,  TSUNG LUNG HUANG ,  CHING-HUA HSIEH ,  CHUNG-SHI LIU ,  CHEN-HUA YU ,  CHIN-YU KU ,  DE-DUI LIAO ,  KUO-CHIO LIU ,  KAI-DI WU ,  KUO-PIN CHANG ,  SHENG-PIN YANG ,  ISAAC HUANG

IPC分类号： H01L23/00 ,  H01L21/78

CPC分类号： H01L24/83 ,  H01L21/6835 ,  H01L21/78 ,  H01L24/03 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/83201 ,  H01L2224/8385 ,  H01L2224/921 ,  H01L2224/94 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/014

摘要： A method of manufacturing a semiconductor structure, comprising: receiving a first substrate including a first surface, a second surface opposite to the first surface and a plurality of conductive bumps disposed over the first surface; receiving a second substrate; disposing an adhesive over the first substrate or the second substrate; heating the adhesive in a first ambiance; bonding the first substrate with the second substrate by applying a force of less than about 10,000N upon the first substrate or the second substrate and heating the adhesive in a second ambiance; and thinning down a thickness of the first substrate from the second surface.

摘要翻译： 一种制造半导体结构的方法，包括：接收包括第一表面，与第一表面相对的第二表面的第一基板和设置在第一表面上的多个导电凸块; 接收第二基板; 在所述第一基板或所述第二基板上设置粘合剂; 以第一种氛围加热粘合剂; 通过在第一基板或第二基板上施加小于约10,000N的力将第一基板与第二基板接合并以第二氛围加热粘合剂; 以及从所述第二表面减薄所述第一基板的厚度。

公开(公告)号：US20160218055A1

公开(公告)日：2016-07-28

申请号：US15092256

申请日：2016-04-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： HSIU-JEN LIN ,  WEN-HSIUNG LU ,  CHENG-TING CHEN ,  HSUAN-TING KUO ,  WEI-YU CHEN ,  MING-DA CHENG ,  CHUNG-SHI LIU

IPC分类号： H01L23/498 ,  H05K1/11

CPC分类号： H01L23/49816 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/0382 ,  H01L2224/03829 ,  H01L2224/03849 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05794 ,  H01L2224/05811 ,  H01L2224/10125 ,  H01L2224/11005 ,  H01L2224/11334 ,  H01L2224/119 ,  H01L2224/1191 ,  H01L2224/13006 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13117 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/812 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/9212 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/351 ,  H05K1/111 ,  H05K3/34 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/01051 ,  H01L2924/01083 ,  H01L2924/01084 ,  H01L2924/01031 ,  H01L2924/01049 ,  H01L2924/01081 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/01028 ,  H01L2924/01074

摘要： The present disclosure provides a semiconductor package includes a contact pad, a device external to the contact pad and a solder bump on the contact pad. The device has a conductive contact pad corresponding to the contact pad. The solder bump connects the contact pad with the conductive contact pad. The solder bump comprises a height from a top of the solder bump to the contact pad; and a width which is a widest dimension of the solder bump in a direction perpendicular to the height. A junction portion of the solder bump in proximity to the contact pad comprises an hourglass shape.

公开(公告)号：US20160126116A1

公开(公告)日：2016-05-05

申请号：US14994689

申请日：2016-01-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： CHUN-CHENG LIN ,  YU-PENG TSAI ,  MENG-TSE CHEN ,  MING-DA CHENG ,  CHUNG-SHI LIU

IPC分类号： H01L21/67 ,  H01L23/544 ,  H01L21/683

CPC分类号： H01L21/67092 ,  H01L21/6838 ,  H01L21/78 ,  H01L23/544 ,  H01L2223/5446 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/3511 ,  H01L2924/00

摘要： A singulation apparatus includes a carrier having a plurality of singulation sites and a scribe line between each of the plurality of singulation sites and an adjacent singulation site. The carrier has a top surface configured to receive a semiconductor substrate thereon. Each of the plurality of singulation sites includes a deformable portion and at least one vacuum hole. The at least one vacuum hole and the deformable portion is configured to form a seal around the at least one vacuum holes when a force is applied. The present disclosure further includes a method of manufacturing semiconductor devices, especially for a singulation process.

摘要翻译： 分割装置包括具有多个切割位置的载体和在多个分割位置中的每一个之间的划线和相邻的分割位点。 载体具有被配置为在其上接收半导体衬底的顶表面。 多个分割位置中的每一个包括可变形部分和至少一个真空孔。 至少一个真空孔和可变形部分构造成当施加力时围绕所述至少一个真空孔形成密封。 本公开还包括一种制造半导体器件的方法，特别是用于切割工艺。