-
公开(公告)号：US20240072419A1
公开(公告)日：2024-02-29
申请号：US18504376
申请日：2023-11-08
Applicant: Intel Corporation
Inventor： Sidharth Dalmia , Jonathan Jensen , Ozgur Inac , Trang Thai , William J. Lambert , Benjamin Jann
CPC classification number: H01Q1/243 , H01Q1/2283 , H01Q9/0414 , H01Q1/38
Abstract: Disclosed herein are integrated circuit (IC) packages, antenna boards, antenna modules, and communication devices (e.g., for millimeter wave communications). For example, in some embodiments, an antenna module may include: a logic die; a radio frequency front-end (RFFE) die in electrical communication with the logic die; and an antenna patch, wherein the RFFE die is closer to the antenna patch than the logic die is to the antenna patch.
-
公开(公告)号：US20230068300A1
公开(公告)日：2023-03-02
申请号：US17412724
申请日：2021-08-26
Applicant: INTEL CORPORATION
Inventor： Krishna Bharath , William J. Lambert , Christopher Schaef , Alexander Lyakhov , Kaladhar Radhakrishnan , Sriram Srinivasan
Abstract: A microelectronic assembly is provided, comprising a first IC die having an electrical load circuit, a second IC die having a portion of a voltage regulator (VR) electrically coupled to the first IC die, a package substrate having inductors of the VR electrically coupled to the first IC die and the second IC die, and a mold compound between the first IC die and the package substrate. The VR receives power at a first voltage from the package substrate and provides power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage. In various embodiments, the second IC die is in the mold compound. In some embodiments, the mold compound and the second IC die are comprised in a discrete interposer electrically coupled to the first IC die with die-to-die interconnects and to the package substrate with die-to-package substrate interconnects.
-
公开(公告)号：US10658765B2
公开(公告)日：2020-05-19
申请号：US16021474
申请日：2018-06-28
Applicant: Intel Corporation
Inventor： Sri Chaitra Jyotsna Chavali , Sanka Ganesan , William J. Lambert , Debendra Mallik , Zhichao Zhang
Abstract: A method of forming a planar antenna on a first substrate. An antenna feedline is formed on a peelable copper film of a carrier. A dielectric with no internal conductive layer is formed on the feedline. A planar antenna is formed on one of two parallel sides of the dielectric and a feed port is formed adjacent the other parallel side. The feedline connects the antenna with the feed port. One plane of the planar antenna is configured for perpendicular attachment to a second substrate. The feedline is connected to the planar antenna by a via through the dielectric. The peelable copper is removed and the structure is etched to produce the planar antenna on the substrate. Two planar antennas on substrates can be perpendicularly attached to another substrate to form side-firing antennas.
-
公开(公告)号：US20200006305A1
公开(公告)日：2020-01-02
申请号：US16022511
申请日：2018-06-28
Applicant: Intel Corporation
Inventor： William J. Lambert , Krishna Bharath , Beomseok Choi , Robert Sankman
IPC: H01L25/18 , H01L25/065 , H02M1/08
Abstract: A semiconductor package includes a first die and a second die. The first die includes a first plurality of compound semiconductor transistors, and where the first die includes a first section of a Power Management Circuitry (PMC). The second die includes a second plurality of transistors that are arranged as a plurality of CMOS (Complementary metal-oxide-semiconductor) circuitries, and where the second die includes a second section of the PMC. The PMC includes a power converter that includes: a plurality of power switches, a plurality of driver circuitries to correspondingly control the plurality of power switches, and a controller to control the driver circuitries. The first section of the PMC in the first die includes the plurality of power switches, and the second section of the PMC in the second die includes at least a part of the controller.
-
公开(公告)号：US20180101207A1
公开(公告)日：2018-04-12
申请号：US15695947
申请日：2017-09-05
Applicant: INTEL CORPORATION
Inventor： Krishna Bharath , Srikrishnan Venkataraman , William J. Lambert , Michael J. Hill , Alexander Slepoy , Dong Zhong , Kaladhar Radhakrishnan , Hector A. Aguirre Diaz , Jonathan P. Douglas
IPC: G06F1/26
CPC classification number: G06F1/26 , G06F1/3203 , H01L23/645 , H02J1/00 , H02M1/14 , H02M3/158 , H02M3/1584 , H02M2001/008 , H02M2003/1586
Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.
-
Patent Agency Ranking
公开(公告)号：US09397071B2
公开(公告)日：2016-07-19
申请号：US14102757
申请日：2013-12-11
Applicant: Intel Corporation
Inventor： Omkar G. Karhade , John S. Guzek , Johanna M. Swan , Christopher J. Nelson , Nitin A. Deshpande , William J. Lambert , Charles A. Gealer , Feras Eid , Islam A. Salama , Kemal Aygun , Sasha N. Oster , Tyler N. Osborn
IPC: H05K7/00 , H01L25/00 , H01L23/00 , H01L25/065 , H01L23/538 , H05K1/18
CPC classification number: H01L25/16 , H01L23/5383 , H01L23/5386 , H01L23/5387 , H01L24/50 , H01L24/86 , H01L25/00 , H01L25/0655 , H01L2224/0405 , H01L2224/04105 , H01L2224/05568 , H01L2224/056 , H01L2224/05647 , H01L2224/29078 , H01L2224/86203 , H01L2224/86815 , H05K1/185 , Y10T29/49155 , H01L2924/00014 , H01L2924/014
Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.
Abstract translation: 本说明书的微电子封装可以包括具有与其电连接的至少一行连接结构的第一微电子器件和具有与其电连接的至少一排连接结构的第二微电子器件，其中所述至少一个 第一微电子器件行与X方向上的至少一个第二微电子器件行内的对应连接结构对准。 包括具有在互连衬底的第一表面上沿x方向延伸的多个电隔离导电迹线的互连衬底的互连可以附接到所述至少一个第一微电子器件连接结构行和所述至少一个第二微电子器件 连接结构行，使得至少一个互连导电迹线形成第一微电子器件连接结构与其对应的第二微电子器件连接结构之间的连接。
-
公开(公告)号：US20250071885A1
公开(公告)日：2025-02-27
申请号：US18944243
申请日：2024-11-12
Applicant: Intel Corporation
Inventor： Sidharth Dalmia , Zhenguo Jiang , William J. Lambert , Kirthika Nahalingam , Swathi Vijayakumar
Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.
-
公开(公告)号：US12200855B2
公开(公告)日：2025-01-14
申请号：US18418513
申请日：2024-01-22
Applicant: Intel Corporation
Inventor： Sidharth Dalmia , Zhenguo Jiang , William J. Lambert , Kirthika Nahalingam , Swathi Vijayakumar
Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.
-
公开(公告)号：US12154710B2
公开(公告)日：2024-11-26
申请号：US17025537
申请日：2020-09-18
Applicant: Intel Corporation
Inventor： Anuj Modi , Huong Do , William J. Lambert , Krishna Bharath , Harish Krishnamurthy
Abstract: Embodiments disclosed herein include power transformers for microelectronic devices. In an embodiment, a power transformer comprises a magnetic core that is a closed loop with an inner dimension and an outer dimension, and a primary winding around the magnetic core. In an embodiment, the primary winding has a first number of first turns connected in series around the magnetic core. In an embodiment, a secondary winding is around the magnetic core, and the secondary winding has a second number of second turns around the magnetic core. In an embodiment, individual ones of the second turns comprise a plurality of secondary segments connected in parallel.
-
公开(公告)号：US20240164010A1
公开(公告)日：2024-05-16
申请号：US18418513
申请日：2024-01-22
Applicant: Intel Corporation
Inventor： Sidharth Dalmia , Zhenguo Jiang , William J. Lambert , Kirthika Nahalingam , Swathi Vijayakumar
CPC classification number: H05K1/0243 , G06F1/1613 , H01F5/04 , H05K1/028 , H05K1/181 , H05K1/189 , H04B1/40
Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.
-
-
-
-
-
-
-
-
-
Search Results
69
records
(took 0.043 seconds)
