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公开(公告)号：US20240154514A1
公开(公告)日：2024-05-09
申请号：US17984183
申请日：2022-11-09
申请人： Intel Corporation
发明人： Nicolas Butzen , Harish Krishnamurthy , Jingshu Yu
CPC分类号： H02M1/0012 , G06F1/08 , G06F1/26 , H02M3/04
摘要： Embodiments herein relate to controlling one or more voltage regulators (VRs) to avoid excessive degradation when a VR increases it current output to supply a hot spot in a compute domain. In one approach, a group of VRs supply current to the domain and each VR's load is monitored to detect an increase in current. A digital controller can reduce the target voltage and/or switching frequency for a VR experiencing an increase in current to equalize the current outputs among the VRs, within a tolerance. In another aspect, a double control loop is used to control a VR. An inner control loop regulates the output of the VR relative to a target voltage and an outer control loop detects the load and adjusts the target voltage and/or switching frequency to avoid excessive degradation.
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公开(公告)号：US11411491B2
公开(公告)日：2022-08-09
申请号：US16642853
申请日：2017-09-29
申请人： Intel Corporation
发明人： Vivek De , Krishnan Ravichandran , Harish Krishnamurthy , Khondker Ahmed , Sriram Vangal , Vaibhav Vaidya , Turbo Majumder , Christopher Schaef , Suhwan Kim , Xiaosen Liu , Nachiket Desai
摘要： Voltage dividing circuitry is provided for use in a voltage converter for converting at least one input Direct Current, DC voltage to a plurality of output DC voltages. The voltage dividing circuitry including a voltage input port to receive an input DC voltage and an inductor having an input-side switch node and an output-side switch node. The output side switch node is connectable to one of a plurality of voltage output ports to supply a converted value of the input DC voltage as an output DC voltage. The flying capacitor interface has a plurality of switching elements and at least one flying capacitor, the flying capacitor interface to divide the input DC voltage to provide a predetermined fixed ratio of the input DC voltage at the input-side switch node of the inductor. A voltage converter and a power management integrated circuit having the voltage dividing circuitry are also provided.
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3.发明申请公开(公告)号：US20190190725A1
公开(公告)日：2019-06-20
申请号：US15846045
申请日：2017-12-18
申请人： Intel Corporation
发明人： Vivek De , Krishnan Ravichandran , Harish Krishnamurthy , Khondker Ahmed , Sriram Vangal , Vaibhav Vaidya , Turbo Majumder , Christopher Schaef , Suhwan Kim , Xiaosen Liu , Nachiket Desai
IPC分类号： H04L9/32
CPC分类号： H04L9/3278
摘要： An apparatus is provided which comprises: an array of physically unclonable function (PUF) devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.
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公开(公告)号：US20190006939A1
公开(公告)日：2019-01-03
申请号：US15638643
申请日：2017-06-30
申请人： INTEL CORPORATION
发明人： Harish Krishnamurthy , Khondker Ahmed , Vivek De , Nachiket Desai , Suhwan Kim , Xiaosen Liu , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav Vaidya , Sriram Vangal
摘要： Embodiments described herein describe operating a master-slave controller. Operating the master-slave controller comprises, based on a determination that the first output voltage value is greater than the second output voltage value, calculating a first duty cycle value and an input voltage value and the second voltage regulator, calculating a second duty cycle value based on the first duty cycle value, and based on a determination that the second output voltage value is greater than or equal to the first output voltage value, calculating the second duty cycle value based on the second output voltage value and the input voltage value and calculating the first duty cycle value based on the second duty cycle value and configuring the first voltage regulator with the first duty cycle value and the second voltage regulator with the second duty cycle value.
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公开(公告)号：US11830829B2
公开(公告)日：2023-11-28
申请号：US17836117
申请日：2022-06-09
申请人： Intel Corporation
发明人： Wilfred Gomes , Mark Bohr , Doug Ingerly , Rajesh Kumar , Harish Krishnamurthy , Nachiket Venkappayya Desai
IPC分类号： H01L23/64 , H01L21/48 , H01L21/56 , H01L23/498 , H01L23/00 , H01L25/065 , H01L25/00
CPC分类号： H01L23/645 , H01L21/4853 , H01L21/565 , H01L23/49838 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06531 , H01L2225/06558 , H01L2225/06582 , H01L2924/19042
摘要： Techniques and mechanisms for providing an inductor with an integrated circuit (IC) die. In an embodiment, the IC die comprises integrated circuitry and one or more first metallization layers. The IC die is configured to couple to a circuit device including one or more second metallization layers, where such coupling results in the formation of an inductor which is coupled to the integrated circuitry. One or more loop structures of the inductor each span both some or all of the one or more first metallization layers and some or all of the one or more second metallization layers. In another embodiment, the IC die or the circuit device includes a ferromagnetic material to concentrate a magnetic flux which is provided with the inductor.
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公开(公告)号：US11675379B2
公开(公告)日：2023-06-13
申请号：US17253096
申请日：2019-09-06
申请人： Intel Corporation
摘要： A Computational Digital Low Dropout (CDLDO) regulator is described that computes a required solution for regulating an output supply as opposed to traditional feedback controllers. The CDLDO regulator is Moore's Law friendly in that it can scale with technology nodes. For example, CDLDO regulator of some embodiments uses a digital approach to voltage regulation, which is orders of magnitude faster than traditional digital LDOs and enables regulation at GHz speeds, making fast dynamic DVFS a reality. The CDLDO also autonomously tunes out the effects of process-voltage-temperature (PVT) and other non-idealities making the settling time totally variation tolerant.
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公开(公告)号：US11336270B2
公开(公告)日：2022-05-17
申请号：US17006726
申请日：2020-08-28
申请人： Intel Corporation
IPC分类号： H03K3/00 , H03K3/037 , H03K5/24 , H03K17/687
摘要： A digital self-start controller, which is functional without fuse and/or trim information. The self-start controller protects a DC-DC converter against large inrush currents and voltage overshoots, while being capable of following a variable VID (voltage identification) reference ramp imposed by the system. The self-start controller uses a relaxation oscillator to set the switching frequency of the DC-DC converter. The oscillator can be initialized using either a clock or current reference to be close to a desired operating frequency. The output of the DC-DC converter is coupled weakly to the oscillator to set the duty cycle for closed loop operation. The controller is naturally biased such that the output supply voltage is always slightly higher than a set point, eliminating the need for any process, voltage, and/or temperature (PVT) imposed trims.
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公开(公告)号：US20220069703A1
公开(公告)日：2022-03-03
申请号：US17009661
申请日：2020-09-01
申请人： Intel Corporation
摘要： A digital control scheme controls an integrator of a PID filter to implement non-linear control of saturating the duty cycle during which the proportional and derivative terms of the PID filter are set to 0 while the integrator and its internal states (previous values or memory) is set to a duty cycle that is the sum of the current nominal duty cycle plus a deltaD. The deltaD is the maximum duty cycle increment that is used to regulate a voltage regulator from ICCmin to ICCmax and is a configuration register that can be set post silicon. An FSM moves from a non-linear all ON state to an open loop duty cycle which maintains the output voltage slightly higher than the required Vref. After a certain period in this open loop, the FSM then ramps down the open loop duty cycle value until the output voltage is close to the Vref.
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9.发明公开公开(公告)号：US20230198384A1
公开(公告)日：2023-06-22
申请号：US17558373
申请日：2021-12-21
申请人： Intel Corporation
IPC分类号： H02M3/07
CPC分类号： H02M3/07
摘要： Techniques and mechanisms for providing an output voltage using any of multiple configurable modes of a switched capacitor voltage regulator (SCVR). In an embodiment, a switched capacitor (SC) voltage converter comprising buses, and cores each coupled to the buses. A first core of the cores comprises a capacitor, and a switch network by which a terminal of the capacitor is to be switchedly coupled to first ones of the buses. Controller circuitry is coupled to operate the SC voltage converter according to a currently configured one of the modes. The modes each correspond to a different respective sequence of switch states to be provided with the switch network. In an embodiment, a first switch state sequence and a second switch state sequence each include a different respective total number of switch states.
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公开(公告)号：US20220069810A1
公开(公告)日：2022-03-03
申请号：US17006726
申请日：2020-08-28
申请人： Intel Corporation
IPC分类号： H03K3/037 , H03K5/24 , H03K17/687
摘要： A digital self-start controller, which is functional without fuse and/or trim information. The self-start controller protects a DC-DC converter against large inrush currents and voltage overshoots, while being capable of following a variable VID (voltage identification) reference ramp imposed by the system. The self-start controller uses a relaxation oscillator to set the switching frequency of the DC-DC converter. The oscillator can be initialized using either a clock or current reference to be close to a desired operating frequency. The output of the DC-DC converter is coupled weakly to the oscillator to set the duty cycle for closed loop operation. The controller is naturally biased such that the output supply voltage is always slightly higher than a set point, eliminating the need for any process, voltage, and/or temperature (PVT) imposed trims.
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