公开(公告)号：US09710422B2

公开(公告)日：2017-07-18

申请号：US14570898

申请日：2014-12-15

Applicant: Intel Corporation

Inventor： Sheldon Weng ,  George E. Matthew ,  Pavan Kumar ,  Wayne L. Proefrock ,  Harish K. Krishnamurthy ,  Krishnan Ravichandran

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/40 ,  G06F1/32 ,  G06F1/26

CPC classification number: G06F13/4282 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3253 ,  G06F13/364 ,  G06F13/404 ,  G06F2213/0052 ,  Y02D10/151

Abstract: Methods and apparatus relating to low cost and/or low overhead serial interface for power management and other IC (Integrated Circuit) devices are described. In an embodiment, a unique address is assigned to each of a plurality of slave devices. The plurality of slave devices are coupled in a daisy chain configuration. And, any access directed at a first slave device from the plurality of slave devices is allowed based at least in part on comparison of an address of the first slave device and an address associated with the access. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220069703A1

公开(公告)日：2022-03-03

申请号：US17009661

申请日：2020-09-01

Applicant: Intel Corporation

Inventor： Harish Krishnamurthy ,  Sheldon Weng ,  Nachiket Desai ,  Suhwan Kim ,  Fabrice Paillet

IPC: H02M3/157 ,  H03H17/02 ,  H02M3/158 ,  G06F1/26

Abstract: A digital control scheme controls an integrator of a PID filter to implement non-linear control of saturating the duty cycle during which the proportional and derivative terms of the PID filter are set to 0 while the integrator and its internal states (previous values or memory) is set to a duty cycle that is the sum of the current nominal duty cycle plus a deltaD. The deltaD is the maximum duty cycle increment that is used to regulate a voltage regulator from ICCmin to ICCmax and is a configuration register that can be set post silicon. An FSM moves from a non-linear all ON state to an open loop duty cycle which maintains the output voltage slightly higher than the required Vref. After a certain period in this open loop, the FSM then ramps down the open loop duty cycle value until the output voltage is close to the Vref.

公开(公告)号：US11658570B2

公开(公告)日：2023-05-23

申请号：US17009661

申请日：2020-09-01

Applicant: Intel Corporation

Inventor： Harish Krishnamurthy ,  Sheldon Weng ,  Nachiket Desai ,  Suhwan Kim ,  Fabrice Paillet

IPC: G06F1/00 ,  H02M3/157 ,  G06F1/26 ,  H02M3/158 ,  H03H17/02

CPC classification number: H02M3/157 ,  G06F1/26 ,  H02M3/1584 ,  H03H17/0211

Abstract: A digital control scheme controls an integrator of a PID filter to implement non-linear control of saturating the duty cycle during which the proportional and derivative terms of the PID filter are set to 0 while the integrator and its internal states (previous values or memory) is set to a duty cycle that is the sum of the current nominal duty cycle plus a deltaD. The deltaD is the maximum duty cycle increment that is used to regulate a voltage regulator from ICCmin to ICCmax and is a configuration register that can be set post silicon. An FSM moves from a non-linear all ON state to an open loop duty cycle which maintains the output voltage slightly higher than the required Vref. After a certain period in this open loop, the FSM then ramps down the open loop duty cycle value until the output voltage is close to the Vref.

公开(公告)号：US09490701B2

公开(公告)日：2016-11-08

申请号：US14325310

申请日：2014-07-07

Applicant: Intel Corporation

Inventor： George E. Matthew ,  Jessica Gullbrand ,  Krishnan Ravichandran ,  Willem M. Beltman ,  Karthik Sankaranarayanan ,  Sheldon Weng ,  Wayne L. Proefrock ,  Harish K. Krishnamurthy ,  Pavan Kumar

IPC: H02M3/157 ,  H02M3/158 ,  H02M3/00 ,  H02M1/44 ,  H02M3/156

CPC classification number: H02M3/158 ,  H02M1/44 ,  H02M3/005 ,  H02M3/157 ,  H02M3/1582 ,  H02M2003/1566

Abstract: Methods and apparatus relating to reducing switching noise and improving transient response in voltage regulators are described. In an embodiment, one or more pulses are inserted into an output waveform of a voltage regulator. The one or more pulses introduce multiple frequencies into the output waveform of the voltage regulator (e.g., to reduce acoustic noise). In another embodiment, the output voltage of a voltage regulator is modified in response to comparison of the output voltage with at least one of a plurality of threshold values. The plurality of threshold values includes an upper trigger point voltage value and a lower trigger point voltage value. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了降低开关噪声和改善稳压器瞬态响应的方法和装置。 在一个实施例中，一个或多个脉冲被插入到电压调节器的输出波形中。 一个或多个脉冲将多个频率引入电压调节器的输出波形（例如，以减少声学噪声）。 在另一个实施例中，响应于输出电压与多个阈值中的至少一个的比较来修改电压调节器的输出电压。 多个阈值包括上触发点电压值和下触发点电压值。 还公开并要求保护其他实施例。