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公开(公告)号：US10530254B2
公开(公告)日：2020-01-07
申请号：US15632086
申请日：2017-06-23
申请人： INTEL CORPORATION
发明人： Khondker Ahmed , Vivek De , Nachiket Desai , Suhwan Kim , Harish Krishnamurthy , Xiaosen Liu , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav Vaidya , Sriram Vangal
摘要： Embodiments described herein concern operating a peak-delivered-power (PDP) controller. Operating a PDP includes calculating the new power output value from the output voltage value and the output current value, determining whether the new power output value is greater than the previous power output value to determine whether the voltage regulator is outputting a maximum power output, based on a determination that the new power output value is greater than the previous power output value, providing an instruction to a duty generator to increase a duty cycle of the voltage regulator, based on a determination that the new power output value is not greater than the previous power output value, providing an instruction to the duty generator to decrease the duty cycle of the voltage regulator, and replacing the previous power output value with the new power output value.
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公开(公告)号：US11675379B2
公开(公告)日：2023-06-13
申请号：US17253096
申请日：2019-09-06
申请人： Intel Corporation
摘要： A Computational Digital Low Dropout (CDLDO) regulator is described that computes a required solution for regulating an output supply as opposed to traditional feedback controllers. The CDLDO regulator is Moore's Law friendly in that it can scale with technology nodes. For example, CDLDO regulator of some embodiments uses a digital approach to voltage regulation, which is orders of magnitude faster than traditional digital LDOs and enables regulation at GHz speeds, making fast dynamic DVFS a reality. The CDLDO also autonomously tunes out the effects of process-voltage-temperature (PVT) and other non-idealities making the settling time totally variation tolerant.
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公开(公告)号：US11429172B2
公开(公告)日：2022-08-30
申请号：US16735563
申请日：2020-01-06
申请人： Intel Corporation
发明人： Alexander Uan-Zo-Li , Eugene Gorbatov , Harish Krishnamurthy , Alexander Lyakhov , Patrick Leung , Stephen Gunther , Arik Gihon , Khondker Ahmed , Philip Lehwalder , Sameer Shekhar , Vishram Pandit , Nimrod Angel , Michael Zelikson
摘要： A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.
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4.发明授权公开(公告)号：US10897364B2
公开(公告)日：2021-01-19
申请号：US15846045
申请日：2017-12-18
申请人： Intel Corporation
发明人： Vivek De , Krishnan Ravichandran , Harish Krishnamurthy , Khondker Ahmed , Sriram Vangal , Vaibhav Vaidya , Turbo Majumder , Christopher Schaef , Suhwan Kim , Xiaosen Liu , Nachiket Desai
IPC分类号： H04L9/32
摘要： Spin Hall Effect (SHE) magneto junction memory cells (e.g., magnetic tunneling junction (MTJ) or spin valve based memory cells) are used to implement high entropy physically unclonable function (PUF) arrays utilizing stochastics interactions of both parameter variations of the SHE-MTJ structures as well as random thermal noises. An apparatus is provided which comprises: an array of PUF devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.
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公开(公告)号：US11411491B2
公开(公告)日：2022-08-09
申请号：US16642853
申请日：2017-09-29
申请人： Intel Corporation
发明人： Vivek De , Krishnan Ravichandran , Harish Krishnamurthy , Khondker Ahmed , Sriram Vangal , Vaibhav Vaidya , Turbo Majumder , Christopher Schaef , Suhwan Kim , Xiaosen Liu , Nachiket Desai
摘要： Voltage dividing circuitry is provided for use in a voltage converter for converting at least one input Direct Current, DC voltage to a plurality of output DC voltages. The voltage dividing circuitry including a voltage input port to receive an input DC voltage and an inductor having an input-side switch node and an output-side switch node. The output side switch node is connectable to one of a plurality of voltage output ports to supply a converted value of the input DC voltage as an output DC voltage. The flying capacitor interface has a plurality of switching elements and at least one flying capacitor, the flying capacitor interface to divide the input DC voltage to provide a predetermined fixed ratio of the input DC voltage at the input-side switch node of the inductor. A voltage converter and a power management integrated circuit having the voltage dividing circuitry are also provided.
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6.发明申请公开(公告)号：US20190190725A1
公开(公告)日：2019-06-20
申请号：US15846045
申请日：2017-12-18
申请人： Intel Corporation
发明人： Vivek De , Krishnan Ravichandran , Harish Krishnamurthy , Khondker Ahmed , Sriram Vangal , Vaibhav Vaidya , Turbo Majumder , Christopher Schaef , Suhwan Kim , Xiaosen Liu , Nachiket Desai
IPC分类号： H04L9/32
CPC分类号： H04L9/3278
摘要： An apparatus is provided which comprises: an array of physically unclonable function (PUF) devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.
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公开(公告)号：US20190006939A1
公开(公告)日：2019-01-03
申请号：US15638643
申请日：2017-06-30
申请人： INTEL CORPORATION
发明人： Harish Krishnamurthy , Khondker Ahmed , Vivek De , Nachiket Desai , Suhwan Kim , Xiaosen Liu , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav Vaidya , Sriram Vangal
摘要： Embodiments described herein describe operating a master-slave controller. Operating the master-slave controller comprises, based on a determination that the first output voltage value is greater than the second output voltage value, calculating a first duty cycle value and an input voltage value and the second voltage regulator, calculating a second duty cycle value based on the first duty cycle value, and based on a determination that the second output voltage value is greater than or equal to the first output voltage value, calculating the second duty cycle value based on the second output voltage value and the input voltage value and calculating the first duty cycle value based on the second duty cycle value and configuring the first voltage regulator with the first duty cycle value and the second voltage regulator with the second duty cycle value.
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公开(公告)号：US20210271277A1
公开(公告)日：2021-09-02
申请号：US17253096
申请日：2019-09-06
申请人： Intel Corporation
摘要： A Computational Digital Low Dropout (CDLDO) regulator is described that computes a required solution for regulating an output supply as opposed to traditional feedback controllers. The CDLDO regulator is Moore's Law friendly in that it can scale with technology nodes. For example, CDLDO regulator of some embodiments uses a digital approach to voltage regulation, which is orders of magnitude faster than traditional digital LDOs and enables regulation at GHz speeds, making fast dynamic DVFS a reality. The CDLDO also autonomously tunes out the effects of process-voltage-temperature (PVT) and other non-idealities making the settling time totally variation tolerant.
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公开(公告)号：US20210208656A1
公开(公告)日：2021-07-08
申请号：US16735563
申请日：2020-01-06
申请人： Intel Corporation
发明人： Alexander Uan-Zo-Li , Eugene Gorbatov , Harish Krishnamurthy , Alexander Lyakhov , Patrick Leung , Stephen Gunther , Arik Gihon , Khondker Ahmed , Philip Lehwalder , Sameer Shekhar , Vishram Pandit , Nimrod Angel , Michael Zelikson
摘要： A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.
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公开(公告)号：US10298117B2
公开(公告)日：2019-05-21
申请号：US15638643
申请日：2017-06-30
申请人： INTEL CORPORATION
发明人： Harish Krishnamurthy , Khondker Ahmed , Vivek De , Nachiket Desai , Suhwan Kim , Xiaosen Liu , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav Vaidya , Sriram Vangal
摘要： Embodiments described herein describe operating a master-slave controller. Operating the master-slave controller comprises, based on a determination that the first output voltage value is greater than the second output voltage value, calculating a first duty cycle value and an input voltage value and the second voltage regulator, calculating a second duty cycle value based on the first duty cycle value, and based on a determination that the second output voltage value is greater than or equal to the first output voltage value, calculating the second duty cycle value based on the second output voltage value and the input voltage value and calculating the first duty cycle value based on the second duty cycle value and configuring the first voltage regulator with the first duty cycle value and the second voltage regulator with the second duty cycle value.
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