公开(公告)号：US20230086149A1

公开(公告)日：2023-03-23

申请号：US17483491

申请日：2021-09-23

申请人： Intel Corporation

发明人： Chia-Hung S. Kuo ,  Deepak Gandiga Shivakumar ,  Anoop Mukker ,  Arik Gihon ,  Zvika Greenfield ,  Asaf Rubinstein ,  Leo Aqrabawi

IPC分类号： G06F12/0804 ,  G06F1/28 ,  G06F1/3206 ,  G06F1/3287

摘要： Some embodiments include apparatuses and electrical models associated with the apparatus. One of the apparatuses includes a power control unit to monitor a power state of the apparatus for entry into a standby mode. The apparatus can include a two-level memory (2LM) hardware accelerator to, responsive to a notification from the power control unit of entry into the standby mode, flush dynamic random access memory (DRAM) content from a first memory part to a second memory part. The apparatus can include processing circuitry to determine memory utilization and move memory from a first memory portion to a second memory portion responsive to memory utilization exceeding a threshold. Other methods systems and apparatuses are described.

公开(公告)号：US20170285703A1

公开(公告)日：2017-10-05

申请号：US15623536

申请日：2017-06-15

申请人： Intel Corporation

发明人： Israel Diamand ,  Asaf Rubinstein ,  Arik Gihon ,  Tal Kuzi ,  Tomer Ziv ,  Nadav Shulman

IPC分类号： G06F1/32 ,  G06F1/26

CPC分类号： G06F1/3296 ,  G06F1/26 ,  G06F1/3228 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

摘要： In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.

公开(公告)号：US20160252952A1

公开(公告)日：2016-09-01

申请号：US14634777

申请日：2015-02-28

申请人： Intel Corporation

发明人： Israel Diamand ,  Asaf Rubinstein ,  Arik Gihon ,  Tal Kuzi ,  Tomer Ziv ,  Nadav Shulman

IPC分类号： G06F1/32

CPC分类号： G06F1/3296 ,  G06F1/26 ,  G06F1/3228 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

摘要： In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括耦合到第一核的第一核和电源管理代理（PMA），以包括存储操作列表的静态表，以及多个列，以指定包括 相应的操作子集。 每个流的执行与第一核的相应状态相关联。 PMA包括控制寄存器（CR），其包括多个存储元件以接收第一值和第二值中的一个。 处理器包括执行逻辑，响应于将第一核放入第一状态的命令，当对应的存储元件存储第一值时，执行第一流的操作，并且当第一流处于 相应的元素存储第二个值。 描述和要求保护其他实施例。

公开(公告)号：US11442529B2

公开(公告)日：2022-09-13

申请号：US16412606

申请日：2019-05-15

申请人： Intel Corporation

发明人： Avinash N. Ananthakrishnan ,  Ameya Ambardekar ,  Ankush Varma ,  Nimrod Angel ,  Nir Rosenzweig ,  Arik Gihon ,  Alexander Gendler ,  Rachid E. Rayess ,  Tamir Salus

IPC分类号： G06F1/00 ,  G06F1/3234 ,  G06F1/3296 ,  G06F9/38 ,  G06F11/34

摘要： In one embodiment, an apparatus comprises: a plurality of intellectual property (IP) circuits, each of the plurality of IP circuits including a configuration register to store a dynamic current budget; and a power controller coupled to the plurality of IP circuits, the power controller including a dynamic current sharing control circuit to receive current throttling hint information regarding a workload to be executed on at least some of the plurality of IP circuits and generate the dynamic current budget for each of the plurality of IP circuits based at least in part thereon. Other embodiments are described and claimed.

公开(公告)号：US20220179473A1

公开(公告)日：2022-06-09

申请号：US17440688

申请日：2020-05-22

申请人： Intel Corporation

发明人： Chen Ranel ,  Christopher J. Lake ,  Hem Doshi ,  Ido Melamed ,  Vijay Degalahal ,  Yevgeni Sabin ,  Reena Patel ,  Yoav Ben-Raphael ,  Nimrod Angel ,  Efraim Rotem ,  Shaun Conrad ,  Tomer Ziv ,  Nir Rosenzweig ,  Esfir Natanzon ,  Yoni Aizik ,  Arik Gihon ,  Natanel Abitan

IPC分类号： G06F1/324

摘要： Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

公开(公告)号：US10228755B2

公开(公告)日：2019-03-12

申请号：US15281806

申请日：2016-09-30

申请人： Intel Corporation

发明人： Doron Rajwan ,  Efraim Rotem ,  Avinash N. Ananthakrishnan ,  Ankush Varma ,  Assaf Ganor ,  Nir Rosenzweig ,  David M. Pawlowski ,  Arik Gihon ,  Nadav Shulman

IPC分类号： G06F1/28 ,  G06F1/32 ,  G06F1/3296

摘要： In an embodiment, a processor includes a power control unit and a plurality of components. A first component of the plurality of components is to receive a power input from a power supply device. The power control unit is to: determine a received voltage at a power input terminal of the first component; determine a voltage difference between the received voltage of the first component and a reliability goal voltage of the first component; determine a running average value based on the voltage difference; and adjust a supply voltage of the power supply device based on the running average value. Other embodiments are described and claimed.

公开(公告)号：US09710054B2

公开(公告)日：2017-07-18

申请号：US14634777

申请日：2015-02-28

申请人： Intel Corporation

发明人： Israel Diamand ,  Asaf Rubinstein ,  Arik Gihon ,  Tal Kuzi ,  Tomer Ziv ,  Nadav Shulman

IPC分类号： G06F1/32 ,  G06F1/26

CPC分类号： G06F1/3296 ,  G06F1/26 ,  G06F1/3228 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

摘要： In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.

公开(公告)号：US11237610B2

公开(公告)日：2022-02-01

申请号：US16689644

申请日：2019-11-20

申请人： Intel Corporation

发明人： Chia-Hung S. Kuo ,  Philip Lehwalder ,  Arik Gihon

IPC分类号： G06F1/30 ,  H02J9/06

摘要： Described are mechanisms and methods for reducing CPU power upon interruption of a supplied power. In some embodiments, an apparatus may comprise an input to receive an indicator that a supply voltage to a computer system has been interrupted. The apparatus may comprise an output to provide an indicator to reduce a processor power consumption level. The apparatus may also comprise a circuitry to establish the indicator to reduce the processor power level based upon the indicator that the supply voltage to the computer system has been interrupted.

公开(公告)号：US20210208656A1

公开(公告)日：2021-07-08

申请号：US16735563

申请日：2020-01-06

申请人： Intel Corporation

发明人： Alexander Uan-Zo-Li ,  Eugene Gorbatov ,  Harish Krishnamurthy ,  Alexander Lyakhov ,  Patrick Leung ,  Stephen Gunther ,  Arik Gihon ,  Khondker Ahmed ,  Philip Lehwalder ,  Sameer Shekhar ,  Vishram Pandit ,  Nimrod Angel ,  Michael Zelikson

IPC分类号： G06F1/32 ,  G05F1/56

摘要： A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

公开(公告)号：US20210149469A1

公开(公告)日：2021-05-20

申请号：US16689644

申请日：2019-11-20

申请人： Intel Corporation

发明人： Chia-Hung S. Kuo ,  Philip Lehwalder ,  Arik Gihon

IPC分类号： G06F1/30 ,  H02J9/06

摘要： Described are mechanisms and methods for reducing CPU power upon interruption of a supplied power. In some embodiments, an apparatus may comprise an input to receive an indicator that a supply voltage to a computer system has been interrupted. The apparatus may comprise an output to provide an indicator to reduce a processor power consumption level. The apparatus may also comprise a circuitry to establish the indicator to reduce the processor power level based upon the indicator that the supply voltage to the computer system has been interrupted.