公开(公告)号：US20220179473A1

公开(公告)日：2022-06-09

申请号：US17440688

申请日：2020-05-22

申请人： Intel Corporation

发明人： Chen Ranel ,  Christopher J. Lake ,  Hem Doshi ,  Ido Melamed ,  Vijay Degalahal ,  Yevgeni Sabin ,  Reena Patel ,  Yoav Ben-Raphael ,  Nimrod Angel ,  Efraim Rotem ,  Shaun Conrad ,  Tomer Ziv ,  Nir Rosenzweig ,  Esfir Natanzon ,  Yoni Aizik ,  Arik Gihon ,  Natanel Abitan

IPC分类号： G06F1/324

摘要： Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

公开(公告)号：US20230418361A1

公开(公告)日：2023-12-28

申请号：US18244748

申请日：2023-09-11

申请人： Intel Corporation

发明人： Chen Ranel ,  Christopher J. Lake ,  Hem Doshi ,  Ido Melamed ,  Vijay Degalahal ,  Yevgeni Sabin ,  Reena Patel ,  Yoav Ben-Raphael ,  Nimrod Angel ,  Efraim Rotem ,  Shaun Conrad ,  Tomer Ziv ,  Nir Rosenzweig ,  Esfir Natanzon ,  Yoni Aizik ,  Arik Gihon ,  Natanel Abitan

IPC分类号： G06F1/324

CPC分类号： G06F1/324

摘要： Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

公开(公告)号：US10379904B2

公开(公告)日：2019-08-13

申请号：US15252511

申请日：2016-08-31

申请人： Intel Corporation

发明人： Eliezer Weissmann ,  Israel Hirsh ,  Efraim Rotem ,  Doron Rajwan ,  Avinash N. Ananthakrishnan ,  Natanel Abitan ,  Ido Melamed ,  Guy M. Therien

IPC分类号： G06F9/46 ,  G06F1/32 ,  G06F9/48 ,  G06F9/50

摘要： In one embodiment, a processor includes: a first storage to store a set of common performance state request settings; a second storage to store a set of thread performance state request settings; and a controller to control a performance state of a first core based on a combination of at least one of the set of common performance state request settings and at least one of the set of thread performance state request settings. Other embodiments are described and claimed.

公开(公告)号：US11789516B2

公开(公告)日：2023-10-17

申请号：US17440688

申请日：2020-05-22

申请人： Intel Corporation

发明人： Chen Ranel ,  Christopher J. Lake ,  Hem Doshi ,  Ido Melamed ,  Vijay Degalahal ,  Yevgeni Sabin ,  Reena Patel ,  Yoav Ben-Raphael ,  Nimrod Angel ,  Efraim Rotem ,  Shaun Conrad ,  Tomer Ziv ,  Nir Rosenzweig ,  Esfir Natanzon ,  Yoni Aizik ,  Arik Gihon ,  Natanel Abitan

IPC分类号： G06F1/00 ,  G06F1/324

CPC分类号： G06F1/324

摘要： Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

公开(公告)号：US20180060123A1

公开(公告)日：2018-03-01

申请号：US15252511

申请日：2016-08-31

申请人： Intel Corporation

发明人： Eliezer Weissmann ,  Israel Hirsh ,  Efraim Rotem ,  Doron Rajwan ,  Avinash N. Ananthakrishnan ,  Natanel Abitan ,  Ido Melamed ,  Guy M. Therien

IPC分类号： G06F9/48

CPC分类号： G06F9/4893 ,  G06F1/32 ,  G06F9/48 ,  G06F9/4806 ,  G06F9/4843 ,  G06F9/485 ,  G06F9/4881 ,  G06F9/50 ,  G06F9/5005 ,  G06F9/5011 ,  G06F9/5016 ,  G06F9/5022 ,  G06F9/5027 ,  G06F9/5044 ,  G06F9/505 ,  G06F9/5094 ,  Y02D10/24

摘要： In one embodiment, a processor includes: a first storage to store a set of common performance state request settings; a second storage to store a set of thread performance state request settings; and a controller to control a performance state of a first core based on a combination of at least one of the set of common performance state request settings and at least one of the set of thread performance state request settings. Other embodiments are described and claimed.