公开(公告)号：US11740682B2

公开(公告)日：2023-08-29

申请号：US17824984

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC: G06F1/00 ,  G06F1/324 ,  G06F1/3296

CPC classification number: G06F1/324 ,  G06F1/3296

Abstract: A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.

公开(公告)号：US20210200293A1

公开(公告)日：2021-07-01

申请号：US17202765

申请日：2021-03-16

Applicant: Intel Corporation

Inventor： Hisham Abu Salah ,  Efraim Rotem ,  Eliezer Weissmann ,  Yoni Aizik ,  Daniel D. Lederman

IPC: G06F1/324 ,  G06F1/3296 ,  G06F1/3206

Abstract: In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.

公开(公告)号：US10990155B2

公开(公告)日：2021-04-27

申请号：US16663658

申请日：2019-10-25

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/324 ,  G06F1/3296

Abstract: A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.

公开(公告)号：US20200012329A1

公开(公告)日：2020-01-09

申请号：US16546441

申请日：2019-08-21

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC: G06F1/324 ,  G06F1/3296

Abstract: In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.

公开(公告)号：US10429919B2

公开(公告)日：2019-10-01

申请号：US15635307

申请日：2017-06-28

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC: G06F1/00 ,  G06F1/324 ,  G06F1/3296

Abstract: A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.

公开(公告)号：US09760158B2

公开(公告)日：2017-09-12

申请号：US14298171

申请日：2014-06-06

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

IPC: G06F1/00 ,  G06F1/32 ,  G06F11/07

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F11/0757 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

公开(公告)号：US20220283619A1

公开(公告)日：2022-09-08

申请号：US17824984

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC: G06F1/324 ,  G06F1/3296

Abstract: In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.

公开(公告)号：US11340687B2

公开(公告)日：2022-05-24

申请号：US17202765

申请日：2021-03-16

Applicant: Intel Corporation

Inventor： Hisham Abu Salah ,  Efraim Rotem ,  Eliezer Weissmann ,  Yoni Aizik ,  Daniel D. Lederman

IPC: G06F1/32 ,  G06F1/324 ,  G06F1/3296 ,  G06F1/3206

Abstract: In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.

公开(公告)号：US09760160B2

公开(公告)日：2017-09-12

申请号：US14722518

申请日：2015-05-27

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Hisham Abu Salah ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Gal Leibovich ,  Yevgeni Sabin ,  Shay Levy

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/00 ,  G06F9/50

CPC classification number: G06F1/3287 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172

Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.

公开(公告)号：US20170090945A1

公开(公告)日：2017-03-30

申请号：US14866584

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Doron Rajwan ,  Eliezer Weissmann ,  Yoni Aizik ,  Itai Feit ,  Tal Kuzi ,  Tomer Ziv ,  Nadav Shulman

IPC: G06F9/44 ,  G06F1/24

CPC classification number: G06F11/3024 ,  G01V11/002 ,  G06F1/3228 ,  G06F1/324 ,  G06F9/5094 ,  G06F11/3058 ,  G06F11/3409 ,  G06F11/3419 ,  G06F11/3452 ,  G06F11/348 ,  G06F2201/88

Abstract: Methods and apparatus relating to techniques for flexible and/or dynamic frequency-related telemetry are described. In an embodiment, logic, coupled to a processor, communicates information to a module. The communicated information includes a duration counter value corresponding to a duration in which an operating characteristic of the processor is controlled. Other embodiments are also disclosed and claimed.