公开(公告)号：US20220179473A1

公开(公告)日：2022-06-09

申请号：US17440688

申请日：2020-05-22

申请人： Intel Corporation

发明人： Chen Ranel ,  Christopher J. Lake ,  Hem Doshi ,  Ido Melamed ,  Vijay Degalahal ,  Yevgeni Sabin ,  Reena Patel ,  Yoav Ben-Raphael ,  Nimrod Angel ,  Efraim Rotem ,  Shaun Conrad ,  Tomer Ziv ,  Nir Rosenzweig ,  Esfir Natanzon ,  Yoni Aizik ,  Arik Gihon ,  Natanel Abitan

IPC分类号： G06F1/324

摘要： Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

公开(公告)号：US10936048B2

公开(公告)日：2021-03-02

申请号：US16369113

申请日：2019-03-29

申请人： Intel Corporation

发明人： Ben Furman ,  Yoni Aizik ,  Robert P. Adler ,  Robert Hesse ,  Chen Ranel

IPC分类号： G06F1/00 ,  G06F1/3296 ,  G06F15/78 ,  G06F9/30 ,  G06F1/3287

摘要： In one embodiment, an apparatus includes a bulk write circuit to generate a bulk write message to send to a destination agent to cause the destination agent to write data comprising register contents into a plurality of registers, at least some of the plurality of registers comprising non-consecutive registers. The bulk write message may include a first message header, a first chunk header including an address of a first register of a first subset of the plurality of registers, and a first payload portion having the register contents for the first subset of the plurality of registers. Other embodiments are described and claimed.

公开(公告)号：US11789516B2

公开(公告)日：2023-10-17

申请号：US17440688

申请日：2020-05-22

申请人： Intel Corporation

发明人： Chen Ranel ,  Christopher J. Lake ,  Hem Doshi ,  Ido Melamed ,  Vijay Degalahal ,  Yevgeni Sabin ,  Reena Patel ,  Yoav Ben-Raphael ,  Nimrod Angel ,  Efraim Rotem ,  Shaun Conrad ,  Tomer Ziv ,  Nir Rosenzweig ,  Esfir Natanzon ,  Yoni Aizik ,  Arik Gihon ,  Natanel Abitan

IPC分类号： G06F1/00 ,  G06F1/324

CPC分类号： G06F1/324

摘要： Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

公开(公告)号：US09684541B2

公开(公告)日：2017-06-20

申请号：US14319099

申请日：2014-06-30

申请人： Intel Corporation

发明人： Eliezer Weissmann ,  Arik Gihon ,  Efraim Rotem ,  Paul S. Diefenbaugh ,  Eric C. Samson ,  Michael Mishaeli ,  Yoni Aizik ,  Chen Ranel

IPC分类号： G06T15/00 ,  G06F9/50 ,  G06F3/14

CPC分类号： G06F9/5044 ,  G06F3/14 ,  G06F9/5083 ,  G09G2360/08

摘要： An apparatus and method for determining thread execution parallelism. For example, a processor in accordance with one embodiment comprises: a plurality of cores to execute a plurality of threads; a plurality of counters to collect data related to the execution of the plurality of threads on the plurality of cores; a dependency analysis module to analyze the data related to the execution of the threads and responsively determine a level of inter-thread dependency; and a control module to responsively adjust operation of the plurality of cores based on the determined level of inter-thread dependency.

公开(公告)号：US20230418361A1

公开(公告)日：2023-12-28

申请号：US18244748

申请日：2023-09-11

申请人： Intel Corporation

发明人： Chen Ranel ,  Christopher J. Lake ,  Hem Doshi ,  Ido Melamed ,  Vijay Degalahal ,  Yevgeni Sabin ,  Reena Patel ,  Yoav Ben-Raphael ,  Nimrod Angel ,  Efraim Rotem ,  Shaun Conrad ,  Tomer Ziv ,  Nir Rosenzweig ,  Esfir Natanzon ,  Yoni Aizik ,  Arik Gihon ,  Natanel Abitan

IPC分类号： G06F1/324

CPC分类号： G06F1/324

摘要： Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

公开(公告)号：US11042213B2

公开(公告)日：2021-06-22

申请号：US16370950

申请日：2019-03-30

申请人： Intel Corporation

发明人： Alexander Gendler ,  Yoni Aizik ,  Chen Ranel ,  Ido Melamed ,  Edward Vaiberman

IPC分类号： G06F1/32 ,  G06F1/3296

摘要： Embodiments include an autonomous core perimeter, configured to save the state of a core of a multi-core processor prior to the processor package being placed into a low-power state. The autonomous core perimeter of each core is configured to save an image of a microcontroller firmware to an external store if it has not been previously saved by another core, along with the unique working state information of that core's microcontroller. Upon restore, the single microcontroller firmware image is retrieved from the external store and pushed to each core along with each core's unique working state.