REDUCING MEMORY POWER USAGE IN FAR MEMORY

    公开(公告)号:US20230086149A1

    公开(公告)日:2023-03-23

    申请号:US17483491

    申请日:2021-09-23

    申请人: Intel Corporation

    摘要: Some embodiments include apparatuses and electrical models associated with the apparatus. One of the apparatuses includes a power control unit to monitor a power state of the apparatus for entry into a standby mode. The apparatus can include a two-level memory (2LM) hardware accelerator to, responsive to a notification from the power control unit of entry into the standby mode, flush dynamic random access memory (DRAM) content from a first memory part to a second memory part. The apparatus can include processing circuitry to determine memory utilization and move memory from a first memory portion to a second memory portion responsive to memory utilization exceeding a threshold. Other methods systems and apparatuses are described.

    AVAILABLE MEMORY OPTIMIZATION TO MANAGE MULTIPLE MEMORY CHANNELS

    公开(公告)号:US20220171551A1

    公开(公告)日:2022-06-02

    申请号:US17673162

    申请日:2022-02-16

    申请人: Intel Corporation

    IPC分类号: G06F3/06

    摘要: Systems, apparatuses, and methods may provide for optimizing the available memory in a power conscious compute platform. For example, a semiconductor apparatus includes logic to communicate with a system memory to divide a plurality of memory channels into functional channels and performance channels. The functional channels are in an active power state during a boot process and the performance channels are in an idle power state during the boot process. The semiconductor apparatus includes logic to track memory usage and bring the performance channels out of the idle power state and into the active power state in response to the tracked memory usage.