公开(公告)号：US20240231473A1

公开(公告)日：2024-07-11

申请号：US18069269

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Patrick Kam-shing Leung ,  Akshay Parnami ,  Jianwei Dai ,  Saranya Sridaran Iyengar ,  Michael F. Mallen

IPC: G06F1/3296 ,  G06F1/3287

CPC classification number: G06F1/3296 ,  G06F1/3287

Abstract: Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to adaptively determining an optimum time frame or demotion threshold for when to power down a voltage rail of an idle device. The demotion threshold is typically the point where the energy cost for maintaining power to the device is approximately the same as or exceeds the energy cost of removing power to the device. The demotion threshold may vary with system conditions and may be based on device leakage current, wake voltage, capacitance, voltage regulator power consumption, current workload and the like. A power control unit in the computing system may manage the voltage of the device and determine the optimum demotion threshold. The power control unit may rely on physical inputs such as fuses on a motherboard, system inputs supplied by a manufacturer, current condition inputs and may be implemented in the device's or the system's software or firmware. By calculating the adaptive demotion threshold, power may be optimized based on platform-to-platform design variation and/or device part-to-part variation.

公开(公告)号：US20220114318A1

公开(公告)日：2022-04-14

申请号：US17557031

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Mark Gallina ,  Jianfang Zhu ,  Kristoffer Fleming ,  Akhllesh Rallabandi ,  Jianwei Dai

IPC: G06F30/39 ,  G01K15/00

Abstract: Methods and apparatus for in-field thermal calibration are disclosed. A disclosed example apparatus includes instructions, memory in the apparatus, and processor circuitry. The processor circuitry is to execute the instructions to determine that a system on chip (SOC) package is deployed, the SOC package deployed with a default first thermal model, in response to the determination that the SOC package is deployed, monitor at least one temperature of the SOC package from a sensor and power usage of the SOC package, calibrate a second thermal model based on the at least one temperature and the power usage, and publish the calibrated second thermal model for control of the SOC package.

公开(公告)号：US20220114136A1

公开(公告)日：2022-04-14

申请号：US17558172

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Jianfang Zhu ,  Ivan Chen ,  Barnes Cooper ,  Jianwei Dai ,  Martin Dixon ,  Kristoffer Fleming ,  Mark Gallina ,  Duncan Glendinning ,  Deepak Samuel Kirubakaran ,  Chia-Hung S. Kuo ,  Yifan Li ,  Adam Norman ,  Michael Rosenzweig ,  Kai P Wang ,  Jin Yan ,  Virendra Vikramsinh Adsure

IPC: G06F15/78 ,  G06F9/445

Abstract: Methods, systems, and apparatus to reconfigure a computer are disclosed. An example electronic device includes at least one memory, instructions in the electronic device, and processor circuitry to execute instructions to analyze data corresponding to a first configuration of the electronic device to detect a change associated with the electronic device, the first configuration corresponding to a respective first user profile, determine a second configuration of the electronic device based on the detected change, and adjust a configuration of the electronic device from the first configuration to the second configuration.

公开(公告)号：US20240085972A1

公开(公告)日：2024-03-14

申请号：US17944310

申请日：2022-09-14

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  Yashwitha Suvarna ,  Boon Hui Ang ,  Pranali Shah

IPC: G06F1/3296 ,  G06F9/52

CPC classification number: G06F1/3296 ,  G06F9/52 ,  G06F2209/5018 ,  G06F2209/5021

Abstract: Embodiments described herein may include apparatus, systems, techniques or processes that are directed to chiplet state aware and dynamic prioritization of voltage regulator event indication handling. An intelligent arbiter notifies chiplets of VR events in a dynamic priority scheme that considers multiple factors such as chiplet state (for example, active, sleep, deep sleep, and the like), chiplet power consumption and time frame for transitioning to an active state, outstanding VR requests, chiplet latency sensitivity and the like in its prioritization of chiplet notifications. As chiplet states themselves are dynamic with a chiplet transitioning between multiple states during operation, the intelligent arbiter may also utilize a dynamic prioritization scheme to maximize efficiency and minimize power consumption.

公开(公告)号：US20230148150A1

公开(公告)日：2023-05-11

申请号：US17664083

申请日：2022-05-19

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  David Pawlowski ,  Adwait Purandare ,  Ankush Varma

IPC: G06F1/3234

CPC classification number: G06F1/3234

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

公开(公告)号：US20220113781A1

公开(公告)日：2022-04-14

申请号：US17557034

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  Jianfang Zhu ,  Ivan Chen ,  Deepak Samuel Kirubakaran ,  Rajshree Chabukswar ,  Richard Winterton ,  Houfei Chen

IPC: G06F1/324

Abstract: Methods and apparatus for bi-directional control of computing unit frequency are disclosed. An example apparatus to control a frequency of a computing unit includes instructions, memory in the apparatus, and processor circuitry. The processor circuitry is to determine a performance hint from a first register, the performance hint corresponding to a requested performance of the computing unit for executing a thread associated with software, determine power and performance (PnP) statistics pertaining to the thread from a second register, control the frequency of the computing unit based on the performance hint and the PnP statistics, and provide a pressure of the computing unit to the software.

公开(公告)号：US20230421048A1

公开(公告)日：2023-12-28

申请号：US17982318

申请日：2022-11-07

Applicant: Intel Corporation

Inventor： Patrick Kam-shing Leung ,  Fazli Lut Ahmad Fu'aad ,  Jianwei Dai ,  Philip Lehwalder

IPC: H02M1/084 ,  H02M1/00

CPC classification number: H02M1/084 ,  H02M1/0048 ,  H02M1/0009

Abstract: Various embodiments provide apparatuses, systems, and methods for automatic phase scaling (APS) of dynamic voltage ID (DVID) in a voltage regulator. Other embodiments may be described and claimed.

公开(公告)号：US20220197367A1

公开(公告)日：2022-06-23

申请号：US17127899

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Deepak S Kirubakaran ,  Ramakrishnan Sivakumar ,  Russell Fenger ,  Monica Gupta ,  Jianwei Dai ,  Premanand Sakarda ,  Guy Therien ,  Rajshree Chabukswar ,  Chad Gutierrez ,  Renji Thomas

IPC: G06F1/3287 ,  G06F1/3228

Abstract: A hardware and software coordinated processor power state policy (e.g., policy for C-state) that delivers optimal power state selection by taking in to account the performance and/or responsiveness needs of thread expected to be scheduled on the core entering idle, to achieve improved IPC and performance for cores running user critical tasks. The scheme provides the ability to deliver responsiveness gains for important and/or user-critical threads running on a system-on-chip. A power management controller coupled to the plurality of processing cores, wherein the power management controller receives a hint from an operating system indicative of a bias towards a power state or performance state for at least one of the processing cores of the plurality of processing cores based on a priority of a thread in context switch.

公开(公告)号：US11366506B2

公开(公告)日：2022-06-21

申请号：US16691873

申请日：2019-11-22

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  David Pawlowski ,  Adwait Purandare ,  Ankush Varma

IPC: G06F1/32 ,  G06F1/3234

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

公开(公告)号：US20200089308A1

公开(公告)日：2020-03-19

申请号：US16691873

申请日：2019-11-22

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  David Pawlowski ,  Adwait Purandare ,  Ankush Varma

IPC: G06F1/3234

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.