-
公开(公告)号：US20220188016A1
公开(公告)日：2022-06-16
申请号：US17558353
申请日：2021-12-21
申请人： Intel Corporation
发明人： Jianwei Dai , Virendra Vikramsinh Adsure , Taeyoung Kim , Chia-Hung S. Kuo , Deepak Gandiga Shivakumar , Amir Ali Radjai , Deepak Samuel Kirubakaran , Jianfang Zhu , Ivan Chen
IPC分类号： G06F3/06
摘要： An example apparatus includes processor circuitry to execute instructions to determine memory usage data associated with a user profile, determine an address hashing policy based on the memory usage data, and determine power states of memory channels based on the address hashing policy.
-
公开(公告)号：US12093573B2
公开(公告)日：2024-09-17
申请号：US17163179
申请日：2021-01-29
申请人： Intel Corporation
发明人： Alaa Alameldeen , Amir Ali Radjai , Jason Van Dyken , Aditya Nagaraja , Joshua Underdown , James Greensky , Wei Wu
CPC分类号： G06F3/0661 , G06F3/0608 , G06F3/0673 , G06F11/1076 , H03M7/30
摘要： An embodiment of an electronic apparatus may include a substrate, and logic coupled to the substrate, the logic to determine a base value to compress a block of data, wherein the block of data consists of a first number of data words, replace original values from a second number of data words from the block of data with respective delta values from the base value to provide compressed data, wherein the second number of data words is at least two less than the first number of data words, and store metadata associated with the block of data together with the compressed data in the block of data. Other embodiments are disclosed and claimed.
-
公开(公告)号：US20210255808A1
公开(公告)日：2021-08-19
申请号：US17163179
申请日：2021-01-29
申请人： Intel Corporation
发明人： Alaa Alameldeen , Amir Ali Radjai , Jason Van Dyken , Aditya Nagaraja , Joshua Underdown , James Greensky , Wei Wu
摘要： An embodiment of an electronic apparatus may include a substrate, and logic coupled to the substrate, the logic to determine a base value to compress a block of data, wherein the block of data consists of a first number of data words, replace original values from a second number of data words from the block of data with respective delta values from the base value to provide compressed data, wherein the second number of data words is at least two less than the first number of data words, and store metadata associated with the block of data together with the compressed data in the block of data. Other embodiments are disclosed and claimed.
-
公开(公告)号：US10754404B2
公开(公告)日：2020-08-25
申请号：US15281299
申请日：2016-09-30
申请人： Intel Corporation
摘要： In an embodiment, a processor includes a first power rail, a first component coupled to the first power rail, and a compensation control unit. The compensation control unit is to: detect a request to change a voltage level of the first power rail by a first voltage change amount; in response to detecting the request, determine that the first voltage change amount exceeds a first threshold level associated with the first component; and in response to determining that the first voltage change amount exceeds the first threshold level, initiate a first compensation action prior to changing the voltage level of the first power rail. Other embodiments are described and claimed.
-
公开(公告)号：US10025732B2
公开(公告)日：2018-07-17
申请号：US15283396
申请日：2016-10-01
申请人： Intel Corporation
摘要： A clock domain crossing can occur earlier in time by detection of when a data signal will coincide with a TSV (time slot valid) signal but the valid signal associated with the data signal will not coincide with a TSV. In response to such a detection, the domain crossing circuit can send the valid signal early, resulting in a valid signal sent on an earlier TSV and the data signal sent on a TSV. In one embodiment, such a system can cause a data signal to be received in a slower clock domain on a first edge of the slower clock signal after the data is queued in the faster clock domain. The sending of the early valid indication can reduce latency in transferring data between clock domains.
-
-
-
-
搜索结果
5 条记录 (耗时 0.014 秒)
