公开(公告)号：US11444148B2

公开(公告)日：2022-09-13

申请号：US16222253

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Gwang-Soo Kim ,  Aaron D. Lilak ,  Kumhyo Byon ,  Doug Ingerly

IPC: H01L49/02 ,  H01F29/14 ,  H01L21/768 ,  H01F27/29 ,  H01F27/28 ,  H01F41/04 ,  H01L27/06

Abstract: An inductor is disclosed. The inductor includes a vertically coiled conductor, a metal contact coupled to a first end of the vertically coiled conductor, and a dielectric material coupled to the metal contact. A tunable high permittivity component is coupled to a second end of the vertically coiled conductor.

公开(公告)号：US11335686B2

公开(公告)日：2022-05-17

申请号：US16669599

申请日：2019-10-31

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Abhishek A. Sharma ,  Tahir Ghani ,  Doug Ingerly ,  Rajesh Kumar

IPC: H01L27/108

Abstract: Described herein are IC devices that include transistors with contacts to one of the source/drain (S/D) regions being on the front side of the transistors and contacts to the other one of the S/D regions being on the back side of the transistors (i.e., “back-side contacts”). Using transistors with one front-side and one back-side S/D contacts provides advantages and enables unique architectures that were not possible with conventional front-end-of-line transistors with both S/D contacts being on one side.

公开(公告)号：US11984430B2

公开(公告)日：2024-05-14

申请号：US18128958

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Mark T. Bohr ,  Wilfred Gomes ,  Rajesh Kumar ,  Pooya Tadayon ,  Doug Ingerly

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/13 ,  H01L2225/06541

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US11854894B2

公开(公告)日：2023-12-26

申请号：US17112697

申请日：2020-12-04

Applicant: Intel Corporation

Inventor： Valluri R. Rao ,  Patrick Morrow ,  Rishabh Mehandru ,  Doug Ingerly ,  Kimin Jun ,  Kevin O'Brien ,  Paul Fischer ,  Szuya S. Liao ,  Bruce Block

IPC: H01L21/822 ,  H01L21/306 ,  H01L21/683 ,  H01L21/8238 ,  H01L21/66 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66 ,  G01R1/073 ,  H01L25/065

CPC classification number: H01L21/8221 ,  H01L21/30625 ,  H01L21/6835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L22/14 ,  H01L23/528 ,  H01L23/53233 ,  H01L24/03 ,  H01L24/05 ,  H01L27/0924 ,  H01L27/1207 ,  H01L29/04 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/20 ,  G01R1/07307 ,  H01L24/08 ,  H01L25/0657 ,  H01L27/1214 ,  H01L27/1222 ,  H01L29/66545 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/08147 ,  H01L2225/06565

Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

公开(公告)号：US11830829B2

公开(公告)日：2023-11-28

申请号：US17836117

申请日：2022-06-09

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mark Bohr ,  Doug Ingerly ,  Rajesh Kumar ,  Harish Krishnamurthy ,  Nachiket Venkappayya Desai

IPC: H01L23/64 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/645 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06558 ,  H01L2225/06582 ,  H01L2924/19042

Abstract: Techniques and mechanisms for providing an inductor with an integrated circuit (IC) die. In an embodiment, the IC die comprises integrated circuitry and one or more first metallization layers. The IC die is configured to couple to a circuit device including one or more second metallization layers, where such coupling results in the formation of an inductor which is coupled to the integrated circuitry. One or more loop structures of the inductor each span both some or all of the one or more first metallization layers and some or all of the one or more second metallization layers. In another embodiment, the IC die or the circuit device includes a ferromagnetic material to concentrate a magnetic flux which is provided with the inductor.

公开(公告)号：US11824041B2

公开(公告)日：2023-11-21

申请号：US17226967

申请日：2021-04-09

Applicant: Intel Corporation

Inventor： Mark T. Bohr ,  Wilfred Gomes ,  Rajesh Kumar ,  Pooya Tadayon ,  Doug Ingerly

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/13 ,  H01L2225/06541

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US20210134802A1

公开(公告)日：2021-05-06

申请号：US16669599

申请日：2019-10-31

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Abhishek A. Sharma ,  Tahir Ghani ,  Doug Ingerly ,  Rajesh Kumar

IPC: H01L27/108

Abstract: Described herein are IC devices that include transistors with contacts to one of the source/drain (S/D) regions being on the front side of the transistors and contacts to the other one of the S/D regions being on the back side of the transistors (i.e., “back-side contacts”). Using transistors with one front-side and one back-side S/D contacts provides advantages and enables unique architectures that were not possible with conventional front-end-of-line transistors with both S/D contacts being on one side.

公开(公告)号：US12074138B2

公开(公告)日：2024-08-27

申请号：US18378978

申请日：2023-10-11

Applicant: Intel Corporation

Inventor： Mark T. Bohr ,  Wilfred Gomes ,  Rajesh Kumar ,  Pooya Tadayon ,  Doug Ingerly

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/13 ,  H01L2225/06541

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US11978727B2

公开(公告)日：2024-05-07

申请号：US16641922

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Sanka Ganesan ,  Doug Ingerly ,  Robert Sankman ,  Mark Bohr ,  Debendra Mallik

IPC: H01L25/10 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058

Abstract: Systems and methods for providing a low profile stacked die semiconductor package in which a first semiconductor package is stacked with a second semiconductor package and both semiconductor packages are conductively coupled to an active silicon substrate that communicably couples the first semiconductor package to the second semiconductor package. The first semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a second interconnect pattern having a second pitch that is greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of wirebonds.

公开(公告)号：US11387198B2

公开(公告)日：2022-07-12

申请号：US16635536

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mark Bohr ,  Doug Ingerly ,  Rajesh Kumar ,  Harish Krishnamurthy ,  Nachiket Venkappayya Desai

IPC: H01L23/64 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: Techniques and mechanisms for providing an inductor with an integrated circuit (IC) die. In an embodiment, the IC die comprises integrated circuitry and one or more first metallization layers. The IC die is configured to couple to a circuit device including one or more second metallization layers, where such coupling results in the formation of an inductor which is coupled to the integrated circuitry. One or more loop structures of the inductor each span both some or all of the one or more first metallization layers and some or all of the one or more second metallization layers. In another embodiment, the IC die or the circuit device includes a ferromagnetic material to concentrate a magnetic flux which is provided with the inductor.