公开(公告)号：US11804475B2

公开(公告)日：2023-10-31

申请号：US18175189

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Cheng-Chieh Hsieh ,  Ming-Yen Chiu

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/16

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L25/105 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/16 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08225 ,  H01L2224/80006 ,  H01L2224/80904 ,  H01L2224/9202 ,  H01L2225/0652 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161

Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.

公开(公告)号：US09613930B2

公开(公告)日：2017-04-04

申请号：US14064093

申请日：2013-10-25

Applicant: Infineon Technologies AG

Inventor： Petteri Palm

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/29 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L24/89 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/295 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/24 ,  H01L24/31 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05018 ,  H01L2224/08112 ,  H01L2224/08137 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/80031 ,  H01L2224/80488 ,  H01L2224/80801 ,  H01L2224/8082 ,  H01L2224/8085 ,  H01L2224/80904 ,  H01L2224/8203 ,  H01L2224/83005 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2224/83851 ,  H01L2224/83889 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

公开(公告)号：US08884414B2

公开(公告)日：2014-11-11

申请号：US13737697

申请日：2013-01-09

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@Eugene Lee ,  Anis Fauzi bin Abdul Aziz ,  Susan Goh Geok Ling ,  Ng Swee Tiang

IPC: H01L23/495 ,  H01L23/34 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L21/56 ,  H01L21/565 ,  H01L21/82 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49551 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/08245 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/73251 ,  H01L2224/80904 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/92222 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/80 ,  H01L2224/16 ,  H01L2224/08 ,  H01L2924/00

Abstract: An integrated circuit module including a generally flat die attachment pad (DAP) positioned substantially in a first plane; and a generally flat lead bar positioned substantially in a second plane above and parallel to said first plane and having at least one downwardly and outwardly extending lead bar lead projecting therefrom and terminating substantially in the first plane; a top leadframe having a plurality of generally flat contact pads positioned substantially in a third plane above and parallel to the second plane and a plurality of leads having proximal end portions connected to the pad portions and having downwardly and outwardly extending distal end portions terminating substantially in said first plane; an IC die connected to the top leadframe, and the DAP; and encapsulation material encapsulating at least portions of the DAP, the lead bar, the top lead frame, and the IC die.

Abstract translation: 一种集成电路模块，包括基本上位于第一平面中的大致平坦的芯片附接焊盘（DAP）; 以及大致平坦的引线条，其基本上位于第二平面的上方并平行于所述第一平面，并且具有至少一个向下和向外延伸的引导杆引线，其从所述第一平面突出并基本上终止在所述第一平面内; 顶部引线框架具有多个基本上平坦的接触焊盘，其基本上位于第三平面中并且平行于第二平面，并且多个引线具有连接到焊盘部分的近端部分，并且具有向下和向外延伸的远端部分，其基本上终止于 第一架飞机 连接到顶部引线框架的IC管芯和DAP; 以及封装材料，其封装DAP，引线条，顶部引线框架和IC管芯的至少一部分。

公开(公告)号：US20230207531A1

公开(公告)日：2023-06-29

申请号：US18175189

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Cheng-Chieh Hsieh ,  Ming-Yen Chiu

IPC: H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L21/568 ,  H01L25/105 ,  H01L23/3677 ,  H01L23/49838 ,  H01L23/49811 ,  H01L23/3128 ,  H01L23/3675 ,  H01L21/4853 ,  H01L2225/06548 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2924/181 ,  H01L2924/15311 ,  H01L2224/80904 ,  H01L24/03

Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.

公开(公告)号：US09831170B2

公开(公告)日：2017-11-28

申请号：US15354447

申请日：2016-11-17

Applicant: DECA Technologies Inc.

Inventor： Christopher M. Scanlan ,  Timothy L. Olson

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/552

CPC classification number: H01L23/49838 ,  H01L21/304 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4867 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L22/14 ,  H01L22/34 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3164 ,  H01L23/48 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/552 ,  H01L23/562 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/03 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05187 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/08225 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/24137 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/80904 ,  H01L2224/81 ,  H01L2224/81395 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/81856 ,  H01L2224/81874 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/0635 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2224/11 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01074 ,  H01L2924/01023 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/04941 ,  H01L2924/0665

Abstract: A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imageable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT).

公开(公告)号：US09806057B2

公开(公告)日：2017-10-31

申请号：US14643831

申请日：2015-03-10

Applicant: DISCO CORPORATION

Inventor： Kazuma Sekiya

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/683

CPC classification number: H01L24/97 ,  H01L21/6835 ,  H01L24/08 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/95 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/08225 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/27334 ,  H01L2224/29194 ,  H01L2224/32225 ,  H01L2224/80143 ,  H01L2224/80385 ,  H01L2224/80904 ,  H01L2224/80907 ,  H01L2224/83002 ,  H01L2224/83143 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/83907 ,  H01L2224/9205 ,  H01L2224/95 ,  H01L2224/95146 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2924/00014 ,  H01L2224/19

Abstract: A chip arranging method for arranging a plurality of chips on a wafer includes a groove forming step of forming a plurality of intersecting grooves that mark off each of chip placement regions on the front surface side of the wafer, a liquid supplying step of supplying a liquid to the chip placement regions, a chip placing step of placing the chips on the liquid to position the chips in the chip placement regions by the surface tension of the liquid after carrying out the liquid supplying step, and a liquid removing step of removing the liquid to arrange the plurality of chips on the wafer after carrying out the chip placing step.

公开(公告)号：US09029194B2

公开(公告)日：2015-05-12

申请号：US14267565

申请日：2014-05-01

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@Eugene Lee ,  Anis Fauzi bin Abdul Aziz ,  Susan Goh Geok Ling ,  Ng Swee Tiang

IPC: H01L21/00 ,  H01L23/495 ,  H01L21/56 ,  H01L21/82 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L21/56 ,  H01L21/565 ,  H01L21/82 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49551 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/08245 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/73251 ,  H01L2224/80904 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/92222 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/80 ,  H01L2224/16 ,  H01L2224/08 ,  H01L2924/00

Abstract: A method of making an integrated circuit module starts with a top leadframe strip comprising a plurality of integrally connected top leadframes. A plurality of flipchip dies are mounted on the top leadframe strip with solder bumps of each flipchip bonded to predetermined pad portions on each of the top leadframes. The top leadframe strip is attached to a bottom leadframe strip. The bottom leadframe strip has a plurality of integrally connected bottom leadframes each having a central die attach pad (DAP) portion and a peripheral frame portion. A back face of each flipchip die contacts the DAP portion of each bottom leadframe. Lead portions of each top leadframe are attached to the peripheral frame portion of each bottom leadframe. The top leadframe strip is attached to the bottom leadframe strip with a back face of each flipchip die contacting the DAP portion of each bottom leadframe and with lead portions of each top leadframe attached to the peripheral frame portion of each bottom leadframe.

Abstract translation: 制造集成电路模块的方法从包括多个整体连接的顶部引线框架的顶部引线框条开始。 多个倒装芯片模具安装在顶部引线框架条上，每个倒装芯片的焊料凸块接合到每个顶部引线框架上的预定焊盘部分。 顶部引线框条连接到底部引线框条。 底部引线框带具有多个整体连接的底部引线框架，每个底部引线框架具有中央管芯附接焊盘（DAP）部分和外围框架部分。 每个倒装芯片模具的背面接触每个底部引线框架的DAP部分。 每个顶部引线框架的引线部分附接到每个底部引线框架的外围框架部分。 顶部引线框条附接到底部引线框条，每个倒装芯片模具的背面接触每个底部引线框架的DAP部分，并且每个顶部引线框架的引线部分连接到每个底部引线框架的外围框架部分。

公开(公告)号：US20150262971A1

公开(公告)日：2015-09-17

申请号：US14643831

申请日：2015-03-10

Applicant: DISCO CORPORATION

Inventor： Kazuma Sekiya

IPC: H01L23/00

CPC classification number: H01L24/97 ,  H01L21/6835 ,  H01L24/08 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/95 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/08225 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/27334 ,  H01L2224/29194 ,  H01L2224/32225 ,  H01L2224/80143 ,  H01L2224/80385 ,  H01L2224/80904 ,  H01L2224/80907 ,  H01L2224/83002 ,  H01L2224/83143 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/83907 ,  H01L2224/9205 ,  H01L2224/95 ,  H01L2224/95146 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2924/00014 ,  H01L2224/19

Abstract: A chip arranging method for arranging a plurality of chips on a wafer includes a groove forming step of forming a plurality of intersecting grooves that mark off each of chip placement regions on the front surface side of the wafer, a liquid supplying step of supplying a liquid to the chip placement regions, a chip placing step of placing the chips on the liquid to position the chips in the chip placement regions by the surface tension of the liquid after carrying out the liquid supplying step, and a liquid removing step of removing the liquid to arrange the plurality of chips on the wafer after carrying out the chip placing step.

Abstract translation: 一种用于在晶片上布置多个芯片的芯片布置方法包括：沟槽形成步骤，形成多个相交槽，用于标记晶片前表面侧上的每个芯片放置区域;液体供应步骤， 到芯片放置区域，在进行液体供给步骤之后，将芯片放置在液体上以通过液体的表面张力将芯片定位在芯片放置区域中的芯片放置步骤，以及去除液体的液体去除步骤 在进行芯片放置步骤之后将多个芯片布置在晶片上。

公开(公告)号：US09029999B2

公开(公告)日：2015-05-12

申请号：US13303166

申请日：2011-11-23

Applicant: Wai Yew Lo

Inventor： Wai Yew Lo

IPC: H01L23/24 ,  H01L25/00 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L25/50 ,  H01L23/49575 ,  H01L24/89 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/80904 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor sensor device is packaged using a footed lid instead of a pre-molded lead frame. A semiconductor sensor die is attached to a first side of a lead frame. The die is then electrically connected to leads of the lead frame. A gel material is dispensed onto the sensor die. The footed lid is attached to the substrate such that the footed lid covers the sensor die and the electrical connections between the die and the lead frame. A molding compound is then formed over the substrate and the footed lid such that the molding compound covers the substrate, the sensor die and the footed lid.

Abstract translation: 半导体传感器装置使用有脚盖而不是预先模制的引线框来封装。 半导体传感器芯片附接到引线框架的第一侧。 然后将管芯电连接到引线框架的引线。 将凝胶材料分配到传感器模具上。 有脚盖被附接到基底上，使得脚踏盖覆盖传感器管芯以及管芯和引线框架之间的电连接。 然后在基材和有脚盖上形成模塑料，使得模塑料覆盖基材，传感器模头和有脚盖。

公开(公告)号：US20140191381A1

公开(公告)日：2014-07-10

申请号：US13737697

申请日：2013-01-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee Han Meng@Eugene Lee ,  Anis Fauzi bin Abdul Aziz ,  Susan Goh Geok Ling ,  Ng Swee Tiang

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L21/56 ,  H01L21/565 ,  H01L21/82 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49551 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/08245 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/73251 ,  H01L2224/80904 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/92222 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/80 ,  H01L2224/16 ,  H01L2224/08 ,  H01L2924/00

Abstract: An integrated circuit module including a generally flat die attachment pad (DAP) positioned substantially in a first plane; and a generally flat lead bar positioned substantially in a second plane above and parallel to said first plane and having at least one downwardly and outwardly extending lead bar lead projecting therefrom and terminating substantially in the first plane; a top leadframe having a plurality of generally flat contact pads positioned substantially in a third plane above and parallel to the second plane and a plurality of leads having proximal end portions connected to the pad portions and having downwardly and outwardly extending distal end portions terminating substantially in said first plane; an IC die connected to the top leadframe, and the DAP; and encapsulation material encapsulating at least portions of the DAP, the lead bar, the top lead frame, and the IC die.

Abstract translation: 一种集成电路模块，包括基本上位于第一平面中的大致平坦的芯片附接焊盘（DAP）; 以及大致平坦的引线条，其基本上位于第二平面的上方并平行于所述第一平面，并且具有至少一个向下和向外延伸的引导杆引线，其从所述第一平面突出并终止于所述第一平面中; 顶部引线框架具有多个基本上平坦的接触焊盘，其基本上位于第三平面中并且平行于第二平面，并且多个引线具有连接到焊盘部分的近端部分，并且具有向下和向外延伸的远端部分，其基本上终止于 第一架飞机 连接到顶部引线框架的IC管芯和DAP; 以及封装材料，其封装DAP，引线条，顶部引线框架和IC管芯的至少一部分。