公开(公告)号：US09638596B2

公开(公告)日：2017-05-02

申请号：US14248324

申请日：2014-04-08

申请人： Wai Yew Lo

发明人： Wai Yew Lo

IPC分类号： G01L9/00 ,  H01L23/495 ,  H01L25/04 ,  G01L19/00 ,  G01L19/06

CPC分类号： G01L9/0052 ,  B81B2201/0228 ,  B81B2201/0264 ,  G01L19/0069 ,  G01L19/06 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/49513 ,  H01L25/041 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A cavity-down pressure sensor device has a pressure-sensing die that is electrically connected to a master control unit (MCU) using face-to-face bonding. Connecting the pressure-sensing die in this manner avoids the need to wire bond the pressure-sensing die to the master control unit.

公开(公告)号：US09297713B2

公开(公告)日：2016-03-29

申请号：US14220121

申请日：2014-03-19

申请人： Wai Yew Lo ,  Lan Chu Tan

发明人： Wai Yew Lo ,  Lan Chu Tan

IPC分类号： H01L29/84 ,  G01L9/00 ,  H01L23/48 ,  H01L23/00 ,  H01L25/16 ,  H01L23/31 ,  H01L21/56

CPC分类号： G01L9/00 ,  G01L17/00 ,  G01L19/147 ,  G01L19/148 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L25/165 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16055 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/1624 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48157 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/92163 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/143 ,  H01L2924/146 ,  H01L2924/16151 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00014

摘要： A semiconductor pressure sensor device having a pressure-sensing die electrically connected to a microcontrol unit (MCU) using either through silicon vias (TSVs) or flip-chip bumps. An active surface of the pressure-sensing die is in facing relationship with the MCU. These embodiments avoid the need to used bonds to electrically connect the pressure-sensing die to the MCU, thereby saving time, reducing size, and reducing cost.

摘要翻译： 一种半导体压力传感器装置，其具有通过硅通孔（TSV）或倒装芯片凸块与微控制单元（MCU）电连接的压力感测管芯。 压敏传感芯片的有源表面与MCU面对关系。 这些实施例避免了使用键将电压连接到MCU的需要，从而节省时间，减小尺寸并降低成本。

公开(公告)号：US20160086880A1

公开(公告)日：2016-03-24

申请号：US14493332

申请日：2014-09-22

申请人： Navas Khan Oratti Kalandar ,  Wai Yew Lo ,  Wen Shi Koh

发明人： Navas Khan Oratti Kalandar ,  Wai Yew Lo ,  Wen Shi Koh

IPC分类号： H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L23/29

CPC分类号： H01L24/81 ,  H01L21/568 ,  H01L23/13 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device includes a semiconductor substrate having opposing first and second main surfaces, a via (TSV) extending from the first main surface of the substrate to the second main surface of the substrate, first electrical connectors formed near the first main surface and second electrical connectors formed near the second main surface. There are insulated bond wires, each extending through the via and having a first end bonded to a respective one of the first electrical connectors and a second end bonded to a respective one of the second electrical connectors. The via may be filled with an encapsulating material.

摘要翻译： 半导体器件包括具有相对的第一和第二主表面的半导体衬底，从衬底的第一主表面延伸到衬底的第二主表面的通孔（TSV），形成在第一主表面附近的第一电连接器和第二电 在第二主表面附近形成连接件。 存在绝缘接合线，每个绝缘接合线都延伸通过通孔，并且具有接合到第一电连接器中的相应一个的第一端和结合到相应的一个第二电连接器的第二端。 通孔可以填充有封装材料。

公开(公告)号：US20150340305A1

公开(公告)日：2015-11-26

申请号：US14281918

申请日：2014-05-20

申请人： Wai Yew Lo

发明人： Wai Yew Lo

IPC分类号： H01L23/495 ,  H01L23/00

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49517 ,  H01L23/49531 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/02 ,  H01L24/19 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A packaged semiconductor device has lead fingers that define a cavity, and a first die located within the cavity. A second die abuts an inactive side of the first die. The second die is electrically connected to one or more of the lead fingers. A redistribution layer abuts an active side of the first die. Metal structures are situated on an outer surface of the redistribution layer. The redistribution layer electrically connects (i) one or more of the metal structures to one or more of the lead fingers and (ii) one or more of the metal structures to one or more bond pads on the active side of the first die.

摘要翻译： 封装的半导体器件具有限定空腔的引线指和位于腔内的第一管芯。 第二个模具邻接第一个模具的非活动侧。 第二管芯电连接到一个或多个引线指。 再分配层邻接第一管芯的有效侧。 金属结构位于再分布层的外表面上。 再分布层将（i）一个或多个金属结构电连接到一个或多个引线指，以及（ii）一个或多个金属结构到第一裸片的有源侧上的一个或多个接合焊盘。

公开(公告)号：US09190352B2

公开(公告)日：2015-11-17

申请号：US14086942

申请日：2013-11-21

申请人： Kong Bee Tiu ,  Teck Beng Lau ,  Wai Yew Lo

发明人： Kong Bee Tiu ,  Teck Beng Lau ,  Wai Yew Lo

IPC分类号： H01L23/495 ,  G01L19/14 ,  H01L23/24 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/49575 ,  G01L19/141 ,  H01L23/24 ,  H01L23/3107 ,  H01L23/315 ,  H01L23/49551 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/16151 ,  H01L2924/16195 ,  H01L2924/167 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device includes a lead frame having a flag and leads that surround the flag. The leads include a dummy lead that has first and second wire bonding areas. A first die is attached on the flag and electrically connected to the first wire bonding area. The first die and the first wire bonding area are encapsulated with a molding material and a cavity with an opening is formed above the first die. The second wire bonding area is exposed in the cavity. A second die is placed in the cavity and electrically connected to the second wire bonding area such that the second die is electrically connected to the first die by way of the dummy lead.

摘要翻译： 半导体器件包括具有标志的引线框和围绕该标记的引线。 引线包括具有第一和第二引线接合区域的虚拟引线。 第一管芯附接在标记上并电连接到第一引线接合区域。 第一管芯和第一引线接合区域用模制材料封装，并且在第一管芯上形成具有开口的空腔。 第二引线接合区域暴露在空腔中。 第二管芯被放置在腔中并电连接到第二引线接合区域，使得第二管芯通过虚拟引线电连接到第一管芯。

公开(公告)号：US20150262924A1

公开(公告)日：2015-09-17

申请号：US14205323

申请日：2014-03-11

申请人： Kong Bee Tiu ,  Chee Seng Foong ,  Wai Yew Lo

发明人： Kong Bee Tiu ,  Chee Seng Foong ,  Wai Yew Lo

IPC分类号： H01L23/495

CPC分类号： H01L23/49558 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49586 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

摘要： A semiconductor package includes a lead frame having an interior region and leads surrounding the interior region, an integrated circuit, a region of insulating material, and a power bar. The integrated circuit, which is disposed in the interior region, has bond pads and electrical couplings (e.g., bond wires) between the bond pads and the leads. The region of insulating material is disposed on at least some of the lead frame leads and the power bar is disposed on the region of insulating material. There also are electrical couplings between the power bar and at least some of the bond pads.

摘要翻译： 半导体封装包括具有内部区域和围绕内部区域的引线的引线框架，集成电路，绝缘材料区域和电源条。 设置在内部区域中的集成电路在接合焊盘和引线之间具有接合焊盘和电耦合（例如，接合线）。 绝缘材料的区域设置在引线框架引线的至少一些上，并且功率条设置在绝缘材料的区域上。 在电源杆和至少一些接合焊盘之间还存在电耦合。

公开(公告)号：US09029999B2

公开(公告)日：2015-05-12

申请号：US13303166

申请日：2011-11-23

申请人： Wai Yew Lo

发明人： Wai Yew Lo

IPC分类号： H01L23/24 ,  H01L25/00 ,  H01L23/00 ,  H01L23/495

CPC分类号： H01L25/50 ,  H01L23/49575 ,  H01L24/89 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/80904 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

摘要： A semiconductor sensor device is packaged using a footed lid instead of a pre-molded lead frame. A semiconductor sensor die is attached to a first side of a lead frame. The die is then electrically connected to leads of the lead frame. A gel material is dispensed onto the sensor die. The footed lid is attached to the substrate such that the footed lid covers the sensor die and the electrical connections between the die and the lead frame. A molding compound is then formed over the substrate and the footed lid such that the molding compound covers the substrate, the sensor die and the footed lid.

摘要翻译： 半导体传感器装置使用有脚盖而不是预先模制的引线框来封装。 半导体传感器芯片附接到引线框架的第一侧。 然后将管芯电连接到引线框架的引线。 将凝胶材料分配到传感器模具上。 有脚盖被附接到基底上，使得脚踏盖覆盖传感器管芯以及管芯和引线框架之间的电连接。 然后在基材和有脚盖上形成模塑料，使得模塑料覆盖基材，传感器模头和有脚盖。

公开(公告)号：US08378435B2

公开(公告)日：2013-02-19

申请号：US12960571

申请日：2010-12-06

申请人： Wai Yew Lo ,  Lan Chu Tan

发明人： Wai Yew Lo ,  Lan Chu Tan

IPC分类号： H01L29/82 ,  H01L21/00

CPC分类号： H01L24/97 ,  G01L19/0069 ,  G01L19/147 ,  H01L24/73 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method of packaging a pressure sensing die includes providing a lead frame with lead fingers and attaching the pressure sensing die to the lead fingers such that bond pads of the die are electrically coupled to the lead fingers and a void is formed between the die and the lead fingers. A gel material is dispensed via an underside of the lead frame into the void such that the gel material substantially fills the void. The gel material is then cured and the die and the lead frame are encapsulated with a mold compound. The finished package does not include a metal lid.

摘要翻译： 一种包装压力传感管芯的方法包括提供具有引线指状物的引线框架并将压力感测裸片连接到引线指，使得管芯的接合焊盘电连接到引线指，并且在管芯和管芯之间形成空隙 铅笔指 凝胶材料通过引线框架的下侧分配到空隙中，使得凝胶材料基本上填充空隙。 然后将凝胶材料固化，并将模具和引线框架用模具化合物包封。 成品包装不包括金属盖。

公开(公告)号：US07955953B2

公开(公告)日：2011-06-07

申请号：US11957486

申请日：2007-12-17

申请人： Wai Yew Lo ,  Heng Keong Yip

发明人： Wai Yew Lo ,  Heng Keong Yip

IPC分类号： H01L21/00 ,  H01L23/495

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/0665 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of packaging semiconductor integrated circuits, including the steps of providing a transfer film and forming a patterned, conductive layer on a surface of the transfer film. A first semiconductor integrated circuit (IC) then is attached to the transfer film, where an active side of the first IC is attached to the transfer film. A second semiconductor IC then is attached to the first IC, where a bottom side of the second IC is attached to a bottom side of the first IC. Die pads on an active surface of the second IC are electrically connected to the conductive layer with wires and then a resin material is provided on one side of the transfer film to encapsulate the first and second ICs, the wires and a portion of the conductive layer. Next the transfer film is removed, which exposes the active side of the first IC and the conductive layer. An electrical distribution layer is formed over the active side of the first IC and the conductive layer and conductive balls are attached to the electrical distribution layer. The conductive balls allow electrical interconnection to the first and second integrated circuits.

摘要翻译： 一种封装半导体集成电路的方法，包括以下步骤：在转印膜的表面上提供转印膜并形成图案化的导电层。 然后，第一半导体集成电路（IC）附接到转印膜，其中第一IC的有源侧附着到转印膜上。 然后，第二半导体IC被附接到第一IC，其中第二IC的底侧附接到第一IC的底侧。 第二IC的有源表面上的焊盘与导体层电连接，然后在转移膜的一侧上设置树脂材料，以封装第一和第二IC，导线和一部分导电层 。 接下来，去除转印膜，其暴露第一IC和导电层的活性侧。 在第一IC的有源侧上形成配电层，导电层和导电球附着在配电层上。 导电球允许与第一和第二集成电路的电互连。

公开(公告)号：US07745260B2

公开(公告)日：2010-06-29

申请号：US12234709

申请日：2008-09-22

申请人： Wai Yew Lo

发明人： Wai Yew Lo

IPC分类号： H01L21/00

CPC分类号： H01L21/568 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of forming a semiconductor package (10) including forming a plurality of cavities (14) in a substrate (12). An electrically conductive pattern (16) is formed on the substrate (12) and over the cavities (14). An electrically insulating layer (22) is formed over the substrate (12) and the electrically conductive pattern (16). A plurality of vias (24) is formed in the electrically insulating layer (22). An integrated circuit (IC) die (28) is attached to the electrically insulating layer (22) and electrically connected to the vias (24) such that the IC die (28) is connected to the electrically conductive pattern (16). A molding operation is performed to encapsulate the IC die (28). The substrate (12) is removed such that the electrically conductive pattern (16) is exposed.

摘要翻译： 一种形成半导体封装（10）的方法，包括在衬底（12）中形成多个空腔（14）。 导电图案（16）形成在基板（12）上并且在空腔（14）之上。 电绝缘层（22）形成在衬底（12）和导电图案（16）之上。 多个通孔（24）形成在电绝缘层（22）中。 集成电路（IC）管芯（28）附接到电绝缘层（22）并电连接到通孔（24），使得IC管芯（28）连接到导电图案（16）。 执行模制操作以封装IC管芯（28）。 去除衬底（12），使得导电图案（16）暴露。